There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

/pdf/rediscovering-black-phosphorus-as-an-anisotropic-layered-40dpp6m2eu.pdf

Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

Designers of VLSI circuits for cryptographic applications are faced with a severe dilemma: Concerns of security, requiring encapsulation of cryptographic applications, and testability, requiring access to all hardware subunits to check for their correct functionality, are basically contradictory. A further security requirement is the immediate detection of failure inside the encryption component. In this paper, an approach based on a compound system test strategy is introduced that reconciles the demands of security and testability. This system test strategy based upon built-in self-test on all levels of implementation allows off-line and concurrent checking without opening access to sensitive regions via test structures. The realization of the system test scheme is a new VLSI cipher implementation, VINCI, that fulfills all security demands for immediate failure detection and supports higher level system test strategies. >

VINCI: Secure test of a VLSI high-speed encryption system

We present a generalized Ramo-Shockley theorem (GRST) for the calculation of time-dependent terminal currents in multidimensional charge transport calculations and simulations. While analytically equivalent to existing boundary integration methods, this new domain integration technique is less sensitive to numerical error introduced by calculations of finite precision. Most significantly, we derive entirely new optimized formulas for the ensemble Monte Carlo estimation of steady-state terminal currents from the time-independent form of our GRST, which are in general not equivalent to the time-average of the true time-dependent terminal currents. We then demonstrate, both analytically and by means of example, how our new variance-minimizing terminal current estimators may be exploited to improve estimator accuracy in comparison to existing methods.

Optimized terminal current calculation for Monte Carlo device simulation

We have fabricated high voltage ( 3.5 kV ) MCT and IGBT devices simultaneously on the same silicon wafer to compare their static and dynamic characteristics. A DMOS technology was adapted to allow for the realization of n-channel ( IGBT ) and p-channel ( MCT ) device structures in the same complimentary DMOS ( CDMOS ) process. The high voltage blocking capability was achieved using the same planar junction termination structure for both types of devices. MOS controlled thyristors offer destinctly lower on-state losses as IGBTs, although low on-state voltages in the range of 2 to 4 V were measured for the IGBT devices with 3.5 kV blocking capability. The maximum turn-off capability was found to be determined by the Si material parameters and is therefore identical for both devices.

Static and dynamic characteristics of high voltage ( 3.5 kV ) IGBT and MCT devices

The results of small-signal or transient analyses from a conventional device simulator (or measured data) can be combined with gradient-fitting techniques to produce smooth spline-based MOSFET charge models for circuit simulation. These techniques are also applicable to shape-from-shading problems. Results based on simulations of some small devices are presented. The comparative efficiencies of the small-signal and transient approach are discussed as well as the relation between the so-called small- and large-signal charges. The role of spline-based table models as against compact analytical models is considered. >

Extracting transistor changes from device simulations by gradient fitting

Sphere decoding (SD) allows the high-dimensional MIMO maximum likelihood detection problem to be solved with significantly lower complexity than other methods. The SD algorithm has, however, mostly only been analyzed with DSP implementations in mind. We show that VLSI implementations call for new performance metrics, analyze the resulting implementation tradeoffs for the decoding of complex signal constellations, and develop design guidelines and a generic architecture. When using the /spl lscr/ /sup /spl infin//-norm for the sphere constraint instead of the /spl lscr/ /sup 2/-norm, significant reductions in circuit complexity and improvements in tree pruning efficiency are possible at a minimum performance penalty. As a proof of concept, a high performance ASIC implementation is presented.

/pdf/performance-tradeoffs-in-the-vlsi-implementation-of-the-yrta9yrfyk.pdf

Wolfgang Fichtner

Papers

VINCI: Secure test of a VLSI high-speed encryption system

Optimized terminal current calculation for Monte Carlo device simulation

Static and dynamic characteristics of high voltage ( 3.5 kV ) IGBT and MCT devices

Extracting transistor changes from device simulations by gradient fitting

Performance tradeoffs in the VLSI implementation of the sphere decoding algorithm