There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

Implementation of High-Order Convolution Algorithms with Low Latency on Silicon Chips

A systematic methodology for the calibration of laser simulation environment is presented. This allows device designers to obtain good agreement between measurements and simulations in short time. The procedure is based on the laser simulator DESSIS-Laser and the TCAD environment GENESISe, which provides pre-processing, post-processing and numerical optimization tools. The device under investigation is a molecular beam epitaxy (MBE) grown InGaAs/AlGaAs narrow stripe laser with graded-index carrier confinement (GRICC) and a single quantum-well (SQW) active region.

A TCAD calibration methodology

Layout optimization of an ESD-protection n-MOSFET by simulation and measurement

Linear and nonlinear transport of holes in orthorhombically strained Si to be used in vertical p-MOSFETs is theoretically analyzed. Strong mobility enhancements compared to unstrained Si by up to a factor of three is found at a Ge content of 40% in the SiGe pillar. The anisotropy in the three Cartesian directions is rather small and the saturation velocity remains unchanged. The enhanced material properties make orthorhombically strained Si attractive for device applications, although the improvements are not as strong as for biaxial tensile strain.

Hole Transport in Orthorhombically Strained Silicon

Secondary electron potential contrast in scanning electron microscopy is proposed as the method of choice for two-dimensional dopant imaging and profiling of wide-band-gap semiconductor devices, including SiC MOSFETs, SiC JFETs, quantum wells, and VCSEL lasers. After a review of the physical principles governing the signal generation, the quantitative capabilities of this technique are assessed with applications to test structures and real devices

Wolfgang Fichtner

Papers

Implementation of High-Order Convolution Algorithms with Low Latency on Silicon Chips

A TCAD calibration methodology

Layout optimization of an ESD-protection n-MOSFET by simulation and measurement

Hole Transport in Orthorhombically Strained Silicon

Dopant Imaging and Profiling of Wide-Band-Gap Devices by Secondary Electron Potential Contrast