There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

A new high voltage IGBT concept with a blocking capability exceeding 4.5 kV is presented in this paper. The device features a conventional planar DMOS cell design. To compensate for the lack of injection enhancement at the cathode, the n-base width is minimized for the required blocking voltage employing a punchthrough design. To avoid the problems related to anode shorts embedded in highly conductive stopping layers, low injection efficiency of the p+emitter at the anode is realized with a homogeneous, transparent emitter layer. The properties of the emitter and buffer layers determine the injection efficiency of the anode and the electrical characteristics of the high voltage IGBTs. Experimental devices were demonstrated switching inductive loads at up to 70 A/cm/sup 2/ at 3 kV without using snubbers. These devices have short circuit ruggedness and endure peak power densities of 2 MW/cm/sup 2/ for several microseconds.

Design considerations and characteristics of rugged punchthrough (PT) IGBTs with 4.5 kV blocking capability

Coherent detection of OFDM signals requires channel state information which can be acquired by transmitting known training symbols and by appropriate channel estimation at the receiver. Focusing on robust algorithms suitable for integration in silicon, a novel channel estimation method is proposed. The algorithm is based on a suboptimal modification to the maximum-likelihood estimator and was designed to enable the use of highly optimized constant-coefficient multipliers that require less area on silicon compared to regular multipliers. The mean square error and the complexity of different estimators are analyzed analytically, while an actual ASIC implementation allows to assess the real-world silicon area requirements for our proposed algorithm.

OFDM channel estimation algorithm and ASIC implementation

Modeling secondary electron images for linewidth measurement by critical dimension scanning electron microscopy

This paper presents a new method for optimizing the performance of a lateral npn-transistor used as ESD protection element. Relying on process modeling and thermo-electrical device simulations we are able to use device-internal quantities such as the electric field or the temperature distribution to find the optimal transistor layout. Guided by simulation we are able to guarantee that the avalanche breakdown propagates properly along a single meander-like collector junction. Experimental result from measurements show that this is crucial for better ESD performance of a space efficient device. Our optimized device reaches 83% of the second breakdown trigger current of a straight device. Compared to a unoptimized meander-like device we could increase its performance by 63%. The good agreement between measurements and simulation for different shapes of transistors validates our methodology and approach to optimization of ESD devices.

Wolfgang Fichtner

Papers

Design considerations and characteristics of rugged punchthrough (PT) IGBTs with 4.5 kV blocking capability

OFDM channel estimation algorithm and ASIC implementation

Modeling secondary electron images for linewidth measurement by critical dimension scanning electron microscopy

Layout optimization of an ESD-protection n-MOSFET by simulation and measurement

Lifetime extrapolation for IGBT modules under realistic operation conditions