There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

We have fabricated MOSFET's with channel lengths as short as 0.1 µm by a modified NMOS process. The devices have been designed according to parameters obtained from numerical simulation. Electron-beam lithography has been used to define patterns at all levels with the negative resist GMC in a tri-level configuration. Heat treatments have been as short as possible to preserve very shallow source-drain junction depths ( L = 0.14 µm, we obtain g_{m} = 180 mS/mm for a gate oxide thickness of 160A.

0.15 &#181;m Channel-length MOSFET's fabricated using e-beam lithography

An extraction method for the effective gate RC-delay of MOS single- and multi-finger structures is introduced by deducing a rule of thumb for the effective poly resistance. In addition to the wiring and parasitic capacitance connected to a gate, this distributed poly resistance in conjunction with the nonlinear gate capacitance can cause an appreciable gate delay (RC/spl sim/1 ns). It is demonstrated for a CMOS output driver circuit that this effect is HBM relevant. Here, circuit simulations are compared to the corresponding TLP measurements. Furthermore, a general CDM-level circuit simulation methodology is presented. To our knowledge for the first time, a CDM current source model accounts for the single pin event character of CDM. Under such stress, the simulation reveals an unexpected large impact of the gate PC-delay formed by the metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown, which was validated by CDM stress tests and physical failure analysis.

ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior

Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 mu W/MHz versus 9.6 mu W/MHz for 0.18mum CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 muW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 muW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of V dd-to-ground paths also contributes to a significant decrease of static consumption.

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

Multiple input/multiple output (MIMO) systems have received great attention to boost the capacity of wireless communication systems. Multiple antennas at the transmitter and receiver are used to exploit the spatial diversity in a rich scattering environment to concurrently transmit multiple data streams in the same frequency band thereby increasing spectral efficiency. Besides the actual MIMO decoder a significant part of the implementation complexity of such a system turns out to be in the receiver front-end. In this paper an efficient implementation of a MIMO receiver frontend based on a modified FDD UMTS downlink is presented. A new method for the efficient realization of a MIMO channel estimation is being introduced. The implementation of the RAKE receiver as well as the frequency-offset estimation is also discussed.

FPGA implementation of a MIMO receiver front-end for the UMTS downlink

The impact of the cathode geometry on conduction and switching properties of high voltage trench gate IGBTs is analysed using mixed mode two-dimensional device and circuit simulation tools. The most effective means to minimize conduction losses by injection enhancement at the cathode is the reduction of the width of the mesa containing n/sup +/ electron emitters and the MOS channel regions. As compared to planar IGBTs, the improvement is most pronounced at higher operating temperatures. If low short circuit current densities are of concern, optimized trench gate geometries also require wide trenches. Trading off conduction losses against turn-off losses, trench gate IGBTs generate approximately 30 to 40% less turn-off losses as planar IGBTs with identical on-state voltage.

Wolfgang Fichtner

Papers

0.15 µm Channel-length MOSFET's fabricated using e-beam lithography

ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

FPGA implementation of a MIMO receiver front-end for the UMTS downlink

On-state and short circuit behaviour of high voltage trench gate IGBTs in comparison with planar IGBTs

Wolfgang Fichtner

Papers

0.15 &#181;m Channel-length MOSFET's fabricated using e-beam lithography

ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

FPGA implementation of a MIMO receiver front-end for the UMTS downlink

On-state and short circuit behaviour of high voltage trench gate IGBTs in comparison with planar IGBTs

0.15 µm Channel-length MOSFET's fabricated using e-beam lithography