There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

In this paper the current characteristics of Si triple-gate nanowire transistors are simulated for different channel orientations. The full-band properties of Si are taken into account via the semi-empirical sp3d5s* tight-binding method. The three-dimensional electrostatic potential is solved self-consistently with the device charge density. This allows the treatment of more realistic transistor structures with rough semiconductor-oxide interfaces along the channel.

Three-Dimensional Full-Band Simulations of Si Nanowire Transistors

Novel wireless communication networks for body mounted sensors explore the use of human tissue as a transmission medium. Electrical signal propagation through the human body requires a deep understanding of the dielectrical properties of human tissue. In this work, the dielectrical properties have been investigated to determine the pathway of current flow through the body with respect to data communication between body mounted sensors. Digital data communication by galvanic coupling in the frequency range up to 1 MHz is presented as a promising approach for wireless intrabody communication.

From Dielectrical Properties of Human Tissue to Intra-Body Communications

We propose a model for point‐defect‐assisted transient diffusion and activation of high‐dose boron implants in silicon. To model transient diffusion, a nonlinear equilibrium clustering model for point defects is used. The activation of boron is modeled as a Fermi‐level‐dependent transformation of inactive dopant clusters to substitutional atoms. Comparison with experimental data shows that this approach can provide a description of both rapid thermal annealing and long‐time furnace annealing steps, with an excellent predictive capability for both chemical and electrically active profiles.

A technology oriented model for transient diffusion and activation of boron in silicon

Keywords: Video compression ; 3D-DCT ; VLSI Reference EPFL-CONF-183232 Record created on 2013-01-22, modified on 2017-05-10

A 3D-DCT real-time video compression system for low complexity single-chip VLSI implementation

In many scientific computing problems, the overall execution time is dominated by the time to solve very large linear systems. Quite often, the matrices are unsymmetric and ill conditioned, with an irregular sparsity structure reflecting the irregular refinement in the discretization grid. With increasing problem size and problem dimension, direct solvers cannot be used because of the huge memory requirements. The performance of preconditioned iterative solvers is largely dominated by memory-related aspects like size, bandwidth, and indirect addressing speed.This article summarizes the experience of the authors on the relationship between memory aspects and performance in real applications in the domain of very large scale integration (VLSI) device simulation. The authors analyze storage requirements of direct and iterative solvers on a statistical data set, and demonstrate performance variations due to memory-related architectural features on a number of computers ranging from workstations to Cray, NEC, ...

Wolfgang Fichtner

Papers

Three-Dimensional Full-Band Simulations of Si Nanowire Transistors

From Dielectrical Properties of Human Tissue to Intra-Body Communications

A technology oriented model for transient diffusion and activation of boron in silicon

A 3D-DCT real-time video compression system for low complexity single-chip VLSI implementation

Memory aspects and performance of iterative solvers