Wolfgang Fichtner

TL;DR: A hardware-efficient VLSI architecture for steering matrix computation using a hardware- optimized SVD algorithm which achieves high processing throughput at low area and shows a 3.5-fold hardware-efficiency gain compared to a reference SVD implementation.

Abstract: We report insight into the deactivation mechanisms of group $\mathrm{V}$ donors in heavily doped silicon. Based on our ab initio calculations, we suggest a three step model for the donor deactivation. In highly $n$-type $\mathrm{Si}$ grown at low temperatures, in the absence of excess native point defects, the intrinsic limit to ${n}_{e}$ seems to rise in part by means of donor deactivating distortions of the silicon lattice in the proximity of two or more donor atoms that share close sites. Also, donor dimers play an important part in the deactivation at high doping concentrations. While the dimers constitute a stable or metastable inactive donor configuration, the lattice distortions lower the donor levels gradually below the impurity band in degenerate silicon. On the other hand, we find that, in general, none of the earlier proposed deactivating donor pair defects is stable at any position of the Fermi level. The lattice distortions may be viewed as a precursor to Frenkel pair generation and donor-vacancy clustering process (step 2) that account for deactivation at elevated temperature and longer annealing times. Ultimately, and most prominently in the case of the large $\mathrm{Sb}$ atoms, precipitation of the donor atoms may set in as the last step of the deactivation process chain.

TL;DR: A lazy-expansion technique for generating small approximate symbolic analog circuit analysis expressions and methods used in SYNAP for eliminating pole and zero movement at the design point and for handling variables representing device mismatches are presented.

TL;DR: In this article, a theoretical and experimental investigation on the electron impact ionization in silicon has been carried out in the temperature range between 300 and 773 K. The model proposed in this paper amply extends the range of simulation tools up to nearly 800 K, which is especially important in order to predict the failure threshold of ESD-protection and power devices.

TL;DR: Efficient VLSI implementations of both Rijndael and Serpent ciphers, implemented by two comparable design teams within the same timeframe using the same fabrication process and EDA tools are presented and evaluated.