There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

A study of the threshold-voltage suitability as an application-related reliability indicator for planar-gate non-punch-through IGBTs.

This paper presents the application of an impedance layer peeling technique to network parameter extraction from finite-difference time-domain (FDTD) simulations. It is shown that the combination of both methods offers a simple and efficient way to analyze lossless linear 1- or 2-port structures. The extraction of equivalent entirely in the time domain and the optimization of lumped element parameters is not necessary. Special attention is paid to the problem of injecting voltage steps with short risetimes into the FDTD grid. Results obtained with this technique are compared to network analyzer measurements and usual FDTD analysis based on scattering parameter extraction.

Signal integrity analysis of interconnects using the FDTD method and a layer peeling technique

The impact of the injection efficiency of unshorted anode p/sup +/emitters on the static and dynamic electrical characteristics of high voltage non-punchthrough IGBTs is analysed using mixed mode two-dimensional device and circuit simulation tools. The results are compared to IGBT device structures with shorted anodes. IGBTs with high and low efficiency anode emitters can be designed to have the same conduction losses despite major differences in the p/sup +/emitter doping profiles and the carrier lifetime. Turn-off losses are in general higher for IGBTs with homogeneous low efficiency emitters. Pushing the trade-off between conduction and turn-off losses to the level set by anode shorted IGBTs is also feasible for homogeneous, low efficiency p/sup +/emitter devices, though it requires approaching the technological limits of injection efficiency and carrier lifetime.

A comparison of emitter concepts for high voltage IGBTs

We present new experimental results on optimally scaled MOSFETs with channel lengths below 0.25 µm. These devices have been fabricated using a modified NMOS process. All patterns have been defined by direct-beam writing using both positive and negative electron resists. The gate oxide thickness of 80A together with properly adjusted ion implantation steps yields device thresholds of 0.5 V. All heat treatments have been kept as short as possible to ensure very shallow source-drain junctions. All contact structures are scaled to 1 × 1 µm window features. Finished devices show excellent performance. Long-channel-like behavior is preserved for supply voltages below 2.5 V. The subthreshold slope is 88 mV/decade. Current drive capabilities are the highest ever reported for silicon MOSFETs. The devices exhibit outstanding transconductance values between 270 and 300 mS/mm.

Optimized MOSFETs with subquartermicron channel lengths

Data communication between body-mounted sensors is progressing towards wireless monitoring networks. In this work, digital data communication by galvanic coupling through the body is presented as a promising approach for wireless intra-body communication. The human body itself serves as the transmission medium of electrical current. Both binary and quadrature phase-shift-keying (BPSK and QPSK) modulated data transmissions are implemented and compared for galvanic coupled links between 2 differential electrode pairs. The adaptive system offers up to 1 mA maximum current amplitude between 10 kHz and 1MHz. Data communication at a rate of up to 64 kbit/s was realized with BER of 10(-4) corresponding to an SNR greater than 6 dB. The novel technology has shown its feasibility in clinical trials. Furthermore, such a low-current approach enables data communication that is more energy-saving than other wireless technologies.

Wolfgang Fichtner

Papers

A study of the threshold-voltage suitability as an application-related reliability indicator for planar-gate non-punch-through IGBTs.

Signal integrity analysis of interconnects using the FDTD method and a layer peeling technique

A comparison of emitter concepts for high voltage IGBTs

Optimized MOSFETs with subquartermicron channel lengths

BPSK&QPSK Modulated Data Communication for Biomedical Monitoring Sensor Network