There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

Full—band Monte Carlo simulations are performed for n—type FinFETs as well as for unstrained—Si and strained—Si fully—depleted (FD) SOI-MOSFETs. Gate lengths of 50 nm down to 10 nm are considered, and a fixed off—current of 100 nA/μzm is in each case ensured by adjusting the silicon film thickness. The FinFET shows the best scaling trend, but the strained-Si FDSOI-MOSFET always involves the largest absolute value for the on—current. However, the on—current decreases upon scaling to 10 nm which might stem from a larger influence of surface roughness scattering in thin Si films affecting most strongly quasi—ballistic transport in strained Si. The feature of a decreasing current is found to be absent in drift—diffusion simulation because this approach does not include quasi—ballistic transport.

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Scalability of FinFETs and Unstrained-Si/Strained-Si FDSOI-MOSFETs

A comparison between non-selfconsistent single-particle Monte Carlo (MC) simulations and measurements of the output characteristics of an 0.1 µm n-MOSFET is presented. First the bulk MC model, which features a new simplified treatment of inelastic acoustic intravalley scattering, is validated by comparison with experimental literature data for mobilities and velocities. The dopant distribution of the MOSFET is obtained from a 2D process simulation, which is calibrated with SIMS and electrical measurements and fine-tuned by a comparison of the measured transfer characteristics in the subthreshold regime with a coupled Schro¨dinger drift-diffusion (DD) simulation. Then the quantum effect is replaced by a shift of the work function and the DD, hydrodynamic (HD) and MC models are adjusted to reproduce the measured drain current in the linear regime. The results of the three models in the non-linear regime are compared without further adjustment to the measured output characteristics. While good agreement is found for the MC model, the on-current is significantly overestimated by the HD model and underestimated by the DD model.

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Comparison of Single-Particle Monte Carlo Simulation with Measured Output Characteristics of an 0.1µm n-MOSFET

Multidimensional geometric modeling for 3D TCAD

In this paper we present a simulation approach for electron transport in single-electron devices based on a weak-coupling formulation for the linear-response transconductance of a quantum dot/reservoir system. A simulation tool devised for the simulation of single-electron transistors has been developed. It provides the equilibrium solution of the nonlinear Poisson equation for the classical charges in the bulk and the self-consistent solution of the 3D-Schrodinger-Poisson equation for the quantum dot. The finite temperature groundstate of the few-electron ensemble in the dot is extracted by evaluation of the Gibbs distribution. The program is coupled to a 3D modeling tool for flexible geometry specification.

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TCAD oriented simulation of single-electron transistors at device level

Modern semiconductor manufacturing technology permits the integration of power integrated circuits with per-chip component densities reaching into the millions. This high-density capability, however, will only be utilized if the design costs can be limited to reasonable levels. Widely accepted for VLSI projects, the use of computer-aided design (CAD) tools has recently become a standard procedure in the development of power technologies and the design of new device structures and circuits. This paper attempts to give an overview of the status quo of CAD tools in power IC design, especially the use of simulation tools and computer- aided layout techniques. We illustrate the possibilities of these tools with examples from a recent MCT design effort.

Wolfgang Fichtner

Papers

Scalability of FinFETs and Unstrained-Si/Strained-Si FDSOI-MOSFETs

Comparison of Single-Particle Monte Carlo Simulation with Measured Output Characteristics of an 0.1µm n-MOSFET

Multidimensional geometric modeling for 3D TCAD

TCAD oriented simulation of single-electron transistors at device level

The Use of Cad Tools in Power Device Optimization