There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

For the 65 nm technology node and beyond, new manufacturability problems are arising that strongly impact device and circuit behavior Among these problems, line-edge and line-width roughness (LER and LWR) are of particular interest as dominant issues affecting parametric yield In this paper, we investigate LWR effects by applying latest generation, full 3D TCAD technology including lithography simulation In addition, our results answer open questions concerning the applicability of 2D slicing approximations vis a vis a 3D modeling effort While LWR has been investigated by TCAD before, our methodology includes a full 3D process simulation (including lithography) without simplifications to generate the final transistor structures

A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology

This paper describes the implementation of the complete baseband processing of an IEEE 802.11a receiver on a design-framework for application specific processors. The underlying generic architecture is described, the computational kernels required for an IEEE 802.11a receiver are analyzed, and suitable processing units and architecture- configurations, to be defined at design-time, are identified. The discussion of the receiver implementation shows that the proposed architecture can meet real-time requirements on a 0.13 mum CMOS process using a clock frequency of 160 MHz. The design demonstrates how the proposed standard-specific reconfigurable architecture is a valid alternative to ASIC and DSP implementations when looking for a balance between performance and flexibility.

An IEEE 802.11a baseband receiver implementation on an application specific processor

We have fabricated very high speed, low power devices and circuits using a submicron NMOS technology. Our results illustrate the electrical behavior of single minimum size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3 GHz divide-by-two counter and a 90 MHz 16 × 16 multiplier.

A submicron NMOS technology suitable for low power high speed circuits

A new built-in screening methodology to achieve zero defects in the automotive environment.

Wavelet algorithms with subsequent encoders are used in the newest image compression standards such as JPEG2000 including EBCOT. The set partitioning in hierarchical trees (SPIHT) algorithm belongs to the next generation of encoders for wavelet-transformed images employing more sophisticated coding. SPIHT utilizes inherent redundancy among wavelet coefficients and is especially suited for electrocardiogram (ECG) data and color image compression. In this work, we present the first VLSI implementation using a modified SPIHT algorithm (MSPIHT). Compression ratios of up to 20:1 for ECG signals lead to acceptable results for visual inspection by medical doctors.

Wolfgang Fichtner

Papers

A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology

An IEEE 802.11a baseband receiver implementation on an application specific processor

A submicron NMOS technology suitable for low power high speed circuits

A new built-in screening methodology to achieve zero defects in the automotive environment.

Silicon Implementation of the SPIHT Algorithm for Compression of ECG Records