There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

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Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

In this work we present a study of the combined effects of the variation of process parameters and geometry in a 65 nm technology through consistent three-dimensional TCAD process and device simulations. Channel lengths and widths together with two critical process parameters obtained through a screening experiment are examined in a 3-level full-factorial design of experiments. The results show an increased impact of process variations for short and narrow structures.

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Analysis of Process-Geometry Modulations through 3D TCAD

Dopant profiling and 2D imaging of device cross-sections have a strategic relevance for the development and for the failure analysis of new devices based on silicon carbide (SiC). Due to the extreme physical properties of SiC, the common electrical dopant profiling techniques have been shown to be poorly reliable. In this work, we report the latest advances in dopant profiling and imaging of SiC by the use of scanning electron and scanning probe microscopy techniques.

Advances in Two-Dimensional Dopant Profiling and Imaging of 4H-SiC Devices

Self-consistent full-band Monte Carlo simulations are employed to compare the performance of nanoscale strained-Si single-gate (SG) and unstrained-Si double-gate (DG) MOSFETs for a gate length of 25 nm. Almost the same on-current as in the DG-MOSFET can be achieved by strain in a SG-MOSFET for the same gate overdrive. This is due to the compensation of the higher electron sheet density in the two inversion channels of the DG-MOSFET by the higher strain-enhanced velocity in the channel of the SG-MOSFET. The on-current of the strained-Si SG-MOSFET is almost 10% larger for a channel orientation along the crystallographic 100 direction than for the 110 direction. This confirms that the on-current is determined by quasi-ballistic transport, because the maximum enhancement of the in-plane velocity in bulk (001)-strained Si in the 100 direction is 5% at medium electric fields (the low-field mobilities and saturation velocities are the same and the difference in the thermal injection velocities is negligibly small), whereas the transient bulk velocity overshoot peak is 30% larger in the 100 direction.

/pdf/strained-si-single-gate-versus-unstrained-si-double-gate-1it72cy5yo.pdf

Strained-Si single-gate versus unstrained-Si double-gate MOSFETs

This paper provides an overview of a real-time multi-user multiple-input multiple-output (MIMO) communication testbed designed for demonstration and assessment of real-world wireless communication aspects. The testbed is built on a modular hardware platform consisting of three different boards and incorporates a MIMO-OFDM-based physical (PHY) layer, an embedded media access controller (MAC), and an Ethernet interface. Due to the modular design of the testbed, it can be used for both, real-time and offline processing experiments with real-world aspects.

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Multi-user MIMO testbed

In this work the optical cavity of a vertical-cavity surface-emitting laser (VCSEL) is analyzed with the goal of performing a coupled electro-optical simulation of the device. For this simulation, the eigenmodes and the eigenvalues of the optical cavity have to be obtained. A common approach is to treat Maxwell's equations in the frequency domain and to solve the resulting algebraic eigenvalue equation. As an alternative, the electromagnetic problem is solved in time-domain. The response of the optical cavity is calculated by the finite-difference time-domain (FDTD) method. The optical wave propagation is modeled rigorously, including evanescent and propagating waves. From the FDTD simulation, a steady state optical intensity pattern is extracted. The eigenvalues of the dominant modes are determined using a Pade type approximation.

Wolfgang Fichtner

Papers

Analysis of Process-Geometry Modulations through 3D TCAD

Advances in Two-Dimensional Dopant Profiling and Imaging of 4H-SiC Devices

Strained-Si single-gate versus unstrained-Si double-gate MOSFETs

Multi-user MIMO testbed

Time-domain Green's functions of realistic VCSEL cavities