There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

/pdf/rediscovering-black-phosphorus-as-an-anisotropic-layered-40dpp6m2eu.pdf

Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0 µW/MHz versus 10.9 µW/MHz and more for 0.25 µm CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1 µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55 nW versus 0.84 nW in CSM and 0.94 nW in Wallace).

/pdf/a-low-power-transmission-gate-based-16-bit-multiplier-for-133sthbgx9.pdf

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

Accurate prediction of very shallow junctions by TCAD tools presents a major challenge which requires process simulation models to be accurately tuned on the basis of two-dimensional (2D) dopant profile measurements. Scanning capacitance microscopy (SCM) provides 2D images with a spatial resolution in the 10 nm range, but the extraction of quantitative doping information from the raw experimental data requires a large reverse simulation effort. A methodology for an efficient 2D constant-dC operating mode SCM simulation is presented in this paper: although the simulation requires to calculate the local C–V characteristics for each measurement point, a very high computing speed has been achieved. The accuracy and the resolution of the constant-dC operating mode using direct inversion in presence of arbitrary doping profiles are discussed.

Computational investigation of the accuracy of constant-dC scanning capacitance microscopy for ultra-shallow doping profile characterization

A novel conductive multilevel resist structure has been employed for the six lithographic steps in an nMOS process to produce devices with micron and submicron channel lengths, Enhancement transistor thresholds of 0.7V and ring oscillator stage., delays of 0.11 ns are obtained.

http://ieeexplore.ieee.org/iel5/9946/31822/01481394.pdf

Electron beam lithography for small MOSFETs

IIB-1 three-dimensional numerical modeling of small-size MOSFETs

The dynamic characteristics of large MCT (MOS controlled thyristor) ensembles have been improved by integrating IGBT (insulated-gated bipolar transistor) cells for turn-on and different schemes of cathode and anode shorting for turn-off Such MCT-IGBT ensembles with integrated shorts are able to turn off 4 A (240 A-cm/sup -2/) at 1000 V in typically 15 mu s in the inductive clamped mode The authors report on the effectiveness of these different approaches and their parasitic influence on the turn-on characteristic and the maximum turn-off current capability The implementation of permanent cathode shorts has lead to an increase of the maximum turn-off current of large MCT ensembles, whereas anode shorting leads to faster turn-off and lower tail currents A careful design of the IGBT turn-on cell and placement is required for proper MOS turn-on even at low anode voltages >

https://ieeexplore.ieee.org/iel5/606/6055/00235479.pdf

Wolfgang Fichtner

Papers

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

Computational investigation of the accuracy of constant-dC scanning capacitance microscopy for ultra-shallow doping profile characterization

Electron beam lithography for small MOSFETs

IIB-1 three-dimensional numerical modeling of small-size MOSFETs

Switching behavior and current handling performance of MCT:IGBT cell ensembles