There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

/pdf/rediscovering-black-phosphorus-as-an-anisotropic-layered-40dpp6m2eu.pdf

Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

An efficient sparse LU factorization algorithm on popular shared memory multiprocessors is presented. Interprocess communication is critically important on these architectures—the algorithm introduces O(n) synchronization events only. No global barrier is used and a completely asynchronous scheduling scheme is one central point of the implementation. The algorithm aims at optimizing the single node performance and minimizing the communication overhead. It has been successfully tested on SUN Enterprise, DEC AlphaServer, SGI Origin 2000, Cray T90, J90, and NEC SX-4 parallel computers, delivering up to 2.3 GFlop/s on an eight processor DEC AlphaServer for medium-size semiconductor device simulations and structural engineering problems.

Scalable Parallel Sparse Factorization with Left-Right Looking Strategy on Shared Memory Multoprocessors

Two-dimensional Dopant Profiling and Imaging of 4H Silicon Carbide Devices by Secondary Electron Potential Contrast

In this work, we investigate the theoretical and the experimental accuracy limits of the delineation of pn junctions by scanning capacitance microscopy. We compare three different techniques basing both on experimental data and on one- and two-dimensional simulations of scanning capacitance measurements of epitaxial and shallow junctions.

Accuracy of scanning capacitance microscopy for the delineation of electrical junctions

A new type of full scale 4.5 kV/3 kA GTO has been developed, fabricated, and electrically characterized. The device utilizes a punchthrough concept with a buffer layer. To avoid the requirement of excessive gate currents for turn-on, the new GTO has a homogeneous anode layer without shorts. The anode has a very low efficiency, which allows efficient extraction of charge during turn-off. With the buffer layer, the new device has a significantly reduced wafer thickness as compared to conventional devices without buffer. This reduces switching as well as on-state losses. The turn-off losses of the best devices were reduced to one third of those of conventional GTOs and, at the same time, the on-state losses were decreased by more than one third.

https://ieeexplore.ieee.org/iel3/3746/10945/00509495.pdf

Punchthrough type GTO with buffer layer and homogeneous low efficiency anode structure

ESD failure mechanisms, specific for charged device model (CDM) stress, are discussed for an input protection structure in a smart power technology showing unexpected dependency of CDM robustness on design variations. This paper demonstrates that factors like package parameters, substrate resistance and parasitic pn-junctions and physical layers have a significant influence on circuits' CDM behavior. The importance of consideration and accurate modeling of these factors for achieving meaningful conclusions for failure mechanisms and CDM robustness from circuit simulation is illustrated. For validation of the proposed simulation setup, results from circuit simulation are compared to measurements and device simulation.

Wolfgang Fichtner

Papers

Scalable Parallel Sparse Factorization with Left-Right Looking Strategy on Shared Memory Multoprocessors

Two-dimensional Dopant Profiling and Imaging of 4H Silicon Carbide Devices by Secondary Electron Potential Contrast

Accuracy of scanning capacitance microscopy for the delineation of electrical junctions

Punchthrough type GTO with buffer layer and homogeneous low efficiency anode structure

Study of CDM specific effects for a smart power input protection structure