There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

/pdf/rediscovering-black-phosphorus-as-an-anisotropic-layered-40dpp6m2eu.pdf

Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring

A novel built-in methodology for screening LDMOS transistors to achieve zero defects in the automotive environment

http://ieeexplore.ieee.org/iel4/5880/15664/00724737.pdf

On The Origin Of Tunneling Currents In Scaled Silicon Devices

The calculation of self-consistent charge densities is not a straightforward task in structures with zero-dimensional confinement. In contrast to the semi-classical case the density of states in a quantum dot depends on the potential. However, this dependence is not explicitly given and Newton-Raphson methods are therefore difficult to employ. In this paper we present a numerical method for the calculation of self-consistent electron densities in a quantum dot weakly coupled to a macroscopic reservoir using a multidimensional secant approach that partially overcomes the numerical limitations intrinsic to single-electron transistor device simulations.

Numerical method for the calculation of self-consistent charge densities of reservoir-coupled quantum dots

Hardware/software co-design usually encounters serious problems to guarantee strong real-time constraints while serving many interrupt routines We present an enhanced register-based RISC processor, which is capable of launching every interrupt routine within two clock cycles This processor is implemented as soft IP-Module and features a customizable instruction set, extensive parameterization, and a synthesis model with separate core and interfaces An automatic derivation of adequate test vectors from the current parameter setting verifies the correct functionality

/pdf/a-parametrizable-hybrid-stack-register-processor-as-soft-32oxepej53.pdf

A parametrizable hybrid stack-register processor as soft intellectual property module

TCAD applications such as multi-dimensional process and device simulations or electromagnetic field calculations rely to a large part on a stable and accurate solution of the underlying physical equations. Well-known examples are the set of six equations that govern hydrodynamic transport in deep submicron devices, or the ensemble of equations for coupled pair diffusion. The quality and sometimes even existence of a numerical solution depends to an overwhelming part on the spatial discretization used in a particular calculation. While mesh quality is an old and well-known problem, it is very often ignored by the user. Driven by the need to simulate increasingly complex semiconductor processes and devices, meshing has certainly moved to the forefront of interest in the TCAD community. Here we want to present a review of new developments in multi-dimensional mesh generation for TCAD applications and concentrate on several specific areas such as promising new algorithms for device mesh generation and grid adaptation for process and device applications.

Wolfgang Fichtner

Papers

A novel built-in methodology for screening LDMOS transistors to achieve zero defects in the automotive environment

On The Origin Of Tunneling Currents In Scaled Silicon Devices

Numerical method for the calculation of self-consistent charge densities of reservoir-coupled quantum dots

A parametrizable hybrid stack-register processor as soft intellectual property module

New developments and old problems in grid generation and adaptation for TCAD applications