Showing papers in "Microprocessors and Microsystems in 2011"

TL;DR: This paper presents a simple and efficient multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure, prior to achieving the exact result.

TL;DR: To make particle swarm optimization algorithm more suitable for solving task assignment problems, particles are represented as integer vectors and a new position update method is developed based on discrete domain.

TL;DR: The extended e-puck robot platform requires minimal effort to integrate the well-known open-source robot control framework Player and provides a powerful and flexible platform for experimental swarm robotics research.

TL;DR: A low-error approximation of the sigmoid function and hyperbolic tangent, which are mainly used to activate the artificial neuron, are proposed based on the piecewise linear method, showing better results than the state-of-the-art.

TL;DR: It is shown that multicast mesh NoC provides the highest performance/cost ratio and consequently it is the most suitable interconnect architecture for configurable neural network implementation.

TL;DR: This work presents the design and implementation of CompOSe, a light-weight (only 1500 lines of code) composable operating system for MPSoCs, and experimentally demonstrates the ability to provide temporal composability, even in the presence of dynamic application behaviour and multiple use cases.

TL;DR: The proposed SVM classifier is found to reduce the number of support vectors by a factor of 1.73 when applied to speaker identification and isolated letter recognition problems and can be adapted for various other SVM based pattern recognition systems.

TL;DR: It is shown in this study that the inter-thread data dependency of shared reads and writes are performance bottlenecks and provides a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.

TL;DR: This work proposes a mechanism for supporting design decisions on energy consumption and performance of embedded system applications and the estimates obtained are 93% close to the respective measures obtained from the real hardware platform.

TL;DR: Experimental results show that the proposed HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC Nand flash memories in parallel can improve performance compared to other solid state disk configurations, composed of either SLCNAND or M LC NAND flash memory alone.

TL;DR: The experiment results show that the proposed multicast AL+RPM algorithm can consume, on average, 14% and 20% less power than bLBDR (a broadcasting-based routing algorithm) and the multiple unicast scheme, respectively and has much lower network latency than the above two approaches.

TL;DR: This study focuses on a multi-path slot allocation method in networks with static resource reservations, in particular TDM NoCs, which provides significant overall gains in terms of increased bandwidth or reduced working frequency or area.

TL;DR: This paper considers a representative template of a modern multi-cluster embedded MPSoC and presents an extensive evaluation of the cost associated with supporting OpenMP on such a machine, investigating several implementation variants that are aware of the memory hierarchy and of the heterogeneous interconnection.

TL;DR: A constrained-random coverage-driven approach is presented and customized to be applied to the novel NI as design under test (DUT), and full code and functional coverage is achieved.

TL;DR: This proposal is based on the virtualization concept and allows us to reduce execution time and network latency in a significant percentage and improves the individual application performance when several applications are simultaneously running.

TL;DR: This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities in microprocessor memory elements with minimum delay and intrusiveness.

TL;DR: Two approximate algorithms are introduced that aim to optimize the area of the MCM operation by taking into account the gate-level implementation of each addition and subtraction operation which realizes a constant multiplication.

TL;DR: This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES, which has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead.

TL;DR: A hybrid approach that combines shared-memory and message passing in a single general-purpose CMP architecture that allows efficient execution of applications developed with both parallel programming approaches is proposed.

TL;DR: This paper proposes three 3D floorplanning methods for a Triplet-based Hierarchical Interconnection Network (THIN) which is a new high performance NoC which is not only a feasible but also a low-power and area-efficient NoC at physical level.

TL;DR: On chip interconnects for multiprocessor turbo decoding are investigated and experimental results show that a Network-on-Chip based decoder made of 16 processing elements can achieve a throughput of several hundreds of Mbps.

TL;DR: A design methodology of a multi-objective application specific processor is proposed by integrating an efficient multi- objective exploration approach with the architecture synthesis process, useful for portable devices and many high end applications.

TL;DR: A parallel architecture that efficiently implements the high computationally demanding core of a matching algorithm based on Band-Limited Phase Only spatial Correlation (BLPOC), performed by two concurrent computational units implemented onto a Stratix II Altera family FPGA is proposed.

TL;DR: A novel routing algorithm that can cope with irregular mesh topologies with Long-Range Links and adapt to run-time LRL insertion and topology reconfiguration is presented and a selection function that uses local topology data to adaptively select optimal paths is presented.

TL;DR: A fuzzy predictive redundancy system that can remove most erroneous faults with a fault-detection algorithm is presented that outperforms well-known average and median voters and shows that it can be an appropriate choice for fault-tolerance in the x-by-wire systems.

TL;DR: This paper capitalizes on the common operator technique to present new common structures for the FFT and FEC decoding algorithms to make the architecture open to future function mapping and adapted to accommodated silicon technology variability through dependable design.

TL;DR: A VLSI microrchitecture of a network-on-chip (NoC) router with a wormhole cut-through switching method is presented in this paper and the concept, on-chip microarchitecture, performance characteristics and interesting transient behaviors of the proposed NoC router that uses the wormhole Cut-Through switching method are presented.

TL;DR: This paper identifies the switch components that limit the switch frequency: the arbiter, and proposes new pipelined switch designs focused in reducing the switch latency.

TL;DR: The proposed DXbar can outperform current bufferless networks with deflecting and dropping protocols while consuming at most half of the power, and achieves at least 20% performance improvement in terms of throughput and latency, and at least20% power saving over buffered networks with virtual channels.

TL;DR: A simulation framework capable of simulating the combination of communication networks with computing cores is established and the results exhibit feasibility and potential of efficiently implementing the full HD MVC decoding on multicore NoC architectures.