Journal ArticleDOI
A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops
S. Au,Bosco Leung +1 more
TLDR
In this paper, a low power, lowvoltage, 12-b 8-kHz bandwidth /spl Sigma/spl Delta/ modulator for high quality voice that consumes only 0.34 mW at 1.95 V-3.3 V supply using standard 1.2-/spl mu/m CMOS technology is described.Abstract:
The design of a low-power, low-voltage, 12-b 8-kHz bandwidth /spl Sigma//spl Delta/ modulator for high-quality voice that consumes only 0.34 mW at 1.95 V supply is described. The modulator employs a special architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multistage /spl Sigma//spl Delta/ modulators, this architecture is very tolerant to the modest dc gain of low voltage op-amps. The architecture, together with special circuit techniques, permits a low-voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2-/spl mu/m CMOS technology.read more
Citations
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Journal ArticleDOI
A 900-mV low-power /spl Delta//spl Sigma/ A/D converter with 77-dB dynamic range
TL;DR: In this paper, the design of a low-voltage and low-power /spl Delta/spl Sigma/ analog-to-digital (A/D) converter is presented.
Journal ArticleDOI
Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration
Gert Cauwenberghs,Gabor C. Temes +1 more
TL;DR: Behavioral simulations on dual-quantization oversampled converters demonstrate near-perfect adaptive correction and significant improvements in signal-to-quantized-noise performance over the uncalibrated case, using as few as 5 FIR coefficients.
Converter with 77-dB Dynamic Range
TL;DR: In this article, the design of a low-voltage and low-power analog-to-digital (A/D) converter is presented, where a third-order single-loop modulator topology is implemented with the differential modified switched op-amp technique.
Journal ArticleDOI
A 13.5-b 1.2-V micropower extended counting A/D converter
TL;DR: In this article, the authors presented a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter with a 0.8-/spl mu/m CMOS, where the converter core including the controller and all reconstruction logic occupies about 1.3/spl times/1 mm/sup 2/of chip area.
Journal ArticleDOI
A 13-bit, 2.2-MS/s, 55-mW multibit cascade /spl Sigma//spl Delta/ modulator in CMOS 0.7-/spl mu/m single-poly technology
TL;DR: This paper presents a CMOS 0.7-/spl mu/m /spl Sigma//spl Delta/ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16.2%, and shows that the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures.
References
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Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Journal ArticleDOI
A high resolution multibit sigma-delta modulator with individual level averaging
Feng Chen,Bosco Leung +1 more
TL;DR: In this article, a second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 /spl mu/m CMOS technology.
Journal ArticleDOI
A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF
TL;DR: In this paper, the authors proposed a solution for compensation, the hybrid nested Miller compensation (HNMC) structure or multipath hybrid nestedMiller compensation (MHNMC), for op amps realized in a standard V/sub th/=0.6 V CMOS process.
Proceedings ArticleDOI
A 10-bit, 20-MS/s, 35-mW pipeline A/D converter
Thomas Byunghak Cho,Paul R. Gray +1 more
TL;DR: In this article, a 10-bit 20-MS/s pipeline A/D converter implemented in 1.2-/spl mu/m CMOS technology achieves a power dissipation of 35 mW at full speed operation.
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