Journal ArticleDOI
A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology
Huaide Wang,Jri Lee +1 more
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TLDR
A 21-Gb/s backplane transceiver has been presented that incorporates half-rate topology with purely digital blocks to substantially reduce power consumption and employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure.Abstract:
A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate topology with purely digital blocks to substantially reduce power consumption. The receiver employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure. The one-tap decision-feedback equalizer merges the summer and the slicer into the flipflop, shortening the feedback path and speeding up the operation considerably. Fabricated in 65-nm CMOS, the transceiver (excluding clock generating PLL and CDR circuits) delivers 21-Gb/s data (231- 1 PRBS) over 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply.read more
Citations
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Journal ArticleDOI
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies
TL;DR: Two ultra-high-speed SerDes dedicated for PAM4 and NRZ data are presented, providing prospective design examples for next-generation 400 GbE.
Journal ArticleDOI
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology
TL;DR: This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s that incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller.
Patent
Decision feedback equalizer and transceiver
TL;DR: In this paper, a decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, and a cross coupled latch branch.
Journal ArticleDOI
A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology
TL;DR: A novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power and a novel LC-based FFE structure is proposed to improve the bandwidth of the delay line and the output combiner.
Proceedings ArticleDOI
A case for globally shared-medium on-chip interconnect
TL;DR: This paper shows that with straight forward optimizations, the traffic between different cores can be kept relatively low, which allows simple shared-medium interconnects to be built using communication circuits driving transmission lines.
References
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Journal ArticleDOI
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology
John F. Bulzacchelli,Mounir Meghelli,Sergey V. Rylov,Woogeun Rhee,Alexander V. Rylyakov,Herschel A. Ainspan,Ben Parker,Michael P. Beakes,Aichin Chung,Troy J. Beukema,Petar Pepeljugoski,Lei Shan,Young H. Kwark,S. Gowda,Daniel J. Friedman +14 more
TL;DR: In this paper, a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications is presented, where a 5-tap decision feedback equalizer is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter.
Journal ArticleDOI
Study of Subharmonically Injection-Locked PLLs
Jri Lee,Huaide Wang +1 more
TL;DR: A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon, which explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue.
Journal ArticleDOI
A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS
Ganesh Balamurugan,Joseph T. Kennedy,Gaurab Banerjee,James E. Jaussi,Mozhgan Mansuri,Frank O'Mahony,Bryan K. Casper,R. Mooney +7 more
TL;DR: A scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps is presented.
Proceedings ArticleDOI
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
Mike Harwood,Nirmal C. Warke,Robert Simpson,Tom Leslie,Ajith Amerasekera,S. Batty,Derek Colman,E. Carr,Venugopal Gopinathan,Stephen Hubbins,Peter Hunt,Andrew Keith Joy,Pulkit Khandelwal,B. Killips,T. Krause,Shaun Lytollis,Andrew Pickering,M. Saxton,D. Sebastio,G. Swanson,Andre Szczepanek,T. Ward,J. D. Williams,R. J. Williams,T. Willwerth +24 more
TL;DR: A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication using a digital 2-tap FFE and 5-tap DFE in the RX to provide channel compensation.
Journal ArticleDOI
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS
TL;DR: This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors.