Journal ArticleDOI
A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology
TLDR
A novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power and a novel LC-based FFE structure is proposed to improve the bandwidth of the delay line and the output combiner.Abstract:
This paper presents a complete 50–64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output combiner reduces the required number of inductors and hence reduces the area. In addition, a novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power. Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.read more
Citations
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Journal ArticleDOI
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology
TL;DR: Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR, which saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers.
Journal ArticleDOI
An Area-Efficient and Tunable Bandwidth- Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling
TL;DR: In this article, an area-efficient and tunable bandwidth extension technique for a wideband CMOS amplifier to handle very high rate (50+ Gb/s) signaling while keeping a low jitter penalty is presented.
Journal ArticleDOI
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS
Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shuai Yuan,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang,Hanjun Jiang +9 more
TL;DR: This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process that implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency.
Journal ArticleDOI
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology
TL;DR: Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described and current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology.
References
More filters
Book
Electronic filter design handbook
TL;DR: This book discusses filter design techniques, components Selection for LC and Active Filters, and how to select the Response Characteristic.
Proceedings ArticleDOI
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
John F. Bulzacchelli,Christian Menolfi,Troy J. Beukema,Daniel W. Storaska,Juergen Hertle,David R. Hanson,Ping-Hsuan Hsieh,Sergey V. Rylov,D. Furrer,Daniele Gardellini,Andrea Prati,Thomas Morf,V. Sharma,R. Kelkar,Herschel A. Ainspan,William R. Kelly,L. R. Chieco,G. A. Ritter,J. A. Sorice,Jon D. Garlett,Robert Callan,Matthias Brandli,P. Buchmann,Marcel Kossel,Thomas Toifl,Daniel J. Friedman +25 more
TL;DR: This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE.
Journal ArticleDOI
Integrated transversal equalizers in high-speed fiber-optic systems
Hui Wu,Jose A. Tierno,Petar Pepeljugoski,Jeremy D. Schaub,S. Gowda,Jeffrey A. Kash,Ali Hajimiri +6 more
TL;DR: In this paper, a seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18/spl mu/m SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links.
Journal ArticleDOI
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$ 16 dB Return Loss Over 10 GHz Bandwidth
Marcel Kossel,Christian Menolfi,Jonas R. Weiss,P. Buchmann,G. von Bueren,L. Rodoni,Thomas Morf,Thomas Toifl,Martin L. Schmatz +8 more
TL;DR: A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology with duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations.
Journal ArticleDOI
A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links
Chih-Kong Ken Yang,Mark Horowitz +1 more
TL;DR: An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing and multiplexing of serial data.