A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

TLDR: The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta–sigma analog-to-digital converters (ADCs).

Abstract: This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta–sigma ( $\Delta \Sigma $ ) analog-to-digital converters (ADCs). The use of a CT incremental $\Delta \Sigma $ ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45- $\mu \text{m}$ pitch achieves a differential nonlinearity (DNL) of +0.79/−0.65 LSB, an integral nonlinearity (INL) of +6.85/−6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of $12.6~\mu \text{s}$ . This detector achieves a CFPN of $181~\mu \text {V}_{\text {rms}}$ , a dark RN of $267~\mu \text {V}_{\text {rms}}$ , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves $3\times $ larger spatial resolution, $1.8\times $ higher pixel rate, $1.9\times $ higher energy-efficiency, and 17 dB higher DR, simultaneously.