Journal ArticleDOI
A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis
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TLDR
In this paper, a general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations, and the model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers.Abstract:
A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.read more
Citations
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Journal ArticleDOI
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation
TL;DR: In this paper, a phase noise cancellation technique and a charge pump linearization technique are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL).
Journal ArticleDOI
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
TL;DR: The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions.
Journal ArticleDOI
A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications
TL;DR: In this paper, a /spl Sigma/spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented, where spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise.
Proceedings ArticleDOI
A Wide-Bandwidth 2.4 GHz ISM Band Fractional- $N$ PLL With Adaptive Phase Noise Cancellation
TL;DR: A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems.
Journal ArticleDOI
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
TL;DR: The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution and is less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL.
References
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Journal ArticleDOI
A general theory of phase noise in electrical oscillators
Ali Hajimiri,Thomas H. Lee +1 more
TL;DR: In this paper, a general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators.
Book
Delta-sigma data converters : theory, design, and simulation
TL;DR: Delta-Sigma Data Converters provides comprehensive coverage of low and high-order single-bit, bandpass, continuous-time, multistage modulators as well as advanced topics, including idle-channel tones, stability, decimation and interpolation filter design, and simulation.
Journal ArticleDOI
Spectra of quantized signals
TL;DR: Quantizing of time, or time division, has found application as a means of multiplexing telephone channels and the more familiar word “sampling” will be used here interchangeably with the rather formidable term “quantization of time”.
Journal ArticleDOI
Delta-sigma modulation in fractional-N frequency synthesis
TL;DR: In this article, a delta-sigma (Delta-Sigma) modulation and fractional-N frequency division technique for indirect digital frequency synthesis using a phase-locked loop (PLL) is described.