Proceedings ArticleDOI
An Efficient Peak Power Reduction Technique for Scan Testing
Meng-Fan Wu,Kai-Shun Hu,Jiun-Lang Huang +2 more
- pp 111-114
TLDR
A low power test pattern generation technique which minimizes the peak power consumption associated with the scan and capture operations and iteratively replaces the high power consumption patterns with low power ones generated by a PODEM-based low power ATPG.Abstract:
Power management is posing serious challenges for scan-based testing. In this paper, we propose a low power test pattern generation technique which minimizes the peak power consumption associated with the scan and capture operations. Given a set of fully specified test patterns, the proposed technique iteratively replaces the high power consumption patterns with low power ones generated by a PODEM-based low power ATPG. The proposed technique has been validated using ISCAS89 benchmark circuits. Compared to a commercial ATPG using high merge ratio and random-fill options, the proposed technique reduces the peak shift and capture power by 27.3% and 19.6%, respectively, and the average power by 49.9%.read more
Citations
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Proceedings ArticleDOI
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing
TL;DR: This work is the first to solve the yield loss caused by excessive power supply noise in at-speed scan testing by proposing a novel integrated ATPG scheme that efficiently and effectively performs compressible X-filling.
Journal ArticleDOI
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment
TL;DR: A novel integrated automatic test pattern generation scheme that efficiently and effectively performs compressible low-capture-power X -filling in the linear-decompressor-based test compression environment is proposed.
Proceedings ArticleDOI
A programmable method for low-power scan shift in SoC integrated circuits
Ran Wang,Bonita Bhaskaran,Karthikeyan Natarajan,Ayub Abdollahian,Kaushik Narayanun,Krishnendu Chakrabarty,Amit Sanghani +6 more
TL;DR: A programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing and a heuristic algorithm to derive optimal result for small-to-medium sized problems is presented.
Journal ArticleDOI
On Reducing Scan Shift Activity at RTL
TL;DR: A DFT-based approach for reducing circuit switching activity during scan shift is proposed, which modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization.
Proceedings ArticleDOI
Low peak power ATPG for n-detection test
TL;DR: A low capture power ATPG and a power-aware test compaction method that reduces the risk of invalid test due to IR-drop and chip overheating and the average power consumption is improved when n becomes larger.
References
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An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
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Proceedings ArticleDOI
Static compaction techniques to control scan vector power dissipation
TL;DR: It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced.
Proceedings ArticleDOI
Minimized power consumption for scan-based BIST
TL;DR: The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage.
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.