An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

Abstract: In the process of computer network communication, there is usually the situation of measuring the instability of data transmission within a specified time, which is the problem of bit error rate (BER). In order to transmit information accurately and reliably, the communication is more secure and the signal is more stable. In general, the corresponding error control measures in the communication network will be taken. Cyclic redundancy check (CRC) algorithm is an effective method to detect network communication errors. In this paper, the application of cyclic redundancy check in computer network communication error detection and control is studied. The proposed CRC algorithm can reduce the error rate of the system by detecting and controlling the errors. In addition, we analyse the principle of CRC algorithm, check rules and the understanding of algorithm programming idea in detail. Finally, the application of CRC algorithm in computer network communication error detection and control is discussed, and the validity of CRC algorithm is verified by experiments.

Abstract: This paper presents the design of a compact pro- tocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI) generated by the electrical transitions, allow for clock recov- ery and maintain direct current (DC) balance. An orthogonal concatenated coding scheme is used for correcting transmission errors using modified Bose–Chaudhuri–Hocquenghem (BCH) code capable of correcting all single bit errors and most of the double-adjacent errors. As a result all burst errors of a length up to 31 bits, and some of the longer group errors, are corrected within 256 bits long packet. The efficiency of the proposed solution equals 46.48%, as 119 out of 256 bits are fully available to the user. The design has been implemented and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit with a data rate of 28.2 Gbps. Sample latency analysis has also been performed so that user could easily carry out calculations for different transmission speed. The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length.

Abstract: This classic reference work is a comprehensive guide to the design, evaluation, and use of reliable computer systems. It includes case studies of reliable systems from manufacturers, such as Tandem, Stratus, IBM, and Digital. It covers special systems such as the Galileo Orbiter fault protection system and AT&T telephone switching system processors.

Abstract: Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output This paper investigates the optimal design of the TMR logic (eg, by cleverly inserting voters) to ensure robustness Four different versions of a TMR digital filter were analyzed by fault injection Faults were randomly inserted straight into the bitstream of the FPGA The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 403% to 098% the number of upsets in the routing able to cause an error in the TMR circuit

Abstract: A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

Abstract: Radiation effects in solid-state microelectronics can be split into two general categories: cumulative effects and single-event effects (SEEs). Cumulative effects produce gradual changes in the operational parameters of the devices, whereas SEEs cause abrupt changes or transient behavior in circuits. The space radiation environment provides a multitude of trapped, solar, and cosmic ray charged particles that cause such effects, interfere with space-system operation, and, in some cases, threaten the survival of such space systems. This article will describe these effects and how their impact may be mitigated in silicon-based microcircuits.

Abstract: The book discusses modern channel coding techniques for wireless communications such as turbo codes, low parity check codes (LDPC), space-time coding, Reed Solomon (RS) codes and convolutional codes Many illustrative examples are included in each chapter for easy understanding of the coding techniques The text is integrated with MATLAB-based programs to enhance the understanding of the subjects underlying theories It includes current topics of increasing importance such as turbo codes, LDPC codes, LT codes, Raptor codes and space-time coding in detail, in addition to the traditional codes such as cyclic codes, BCH and RS codes and convolutional codes MIMO communications is a multiple antenna technology, which is an effective method for high-speed or high-reliability wireless communications PC-based MATLAB m-files for the illustrative examples are included and also provided on the accompanying CD, which will help students and researchers involved in advanced and current concepts in coding theory Channel coding, the core of digital communication and data storage, has undergone a major revolution as a result of the rapid growth of mobile and wireless communicationsThe book is divided into 11 chapters Assuming no prior knowledge in the field of channel coding, the opening chapters (1 - 2) begin with basic theory and discuss how to improve the performance of wireless communication channels usingchannel coding Chapters 3 and 4 introduce Galois fields and present detailed coverage of BCH codes and Reed-Solomon codes Chapters 57 introduce the family of convolutional codes, hard and soft-decision Viterbi algorithms, turbo codes, BCJR algorithm for turbo decoding and studies trellis coded modulation (TCM), turbo trellis coded modulation (TTCM), bit-interleaved coded modulation (BICM) as well as iterative BICM (BICM-ID) and compares them under various channel conditions Chapters 8 and 9 focus on low-density parity-check (LDPC) codes, LT codes and Raptor codes Chapters 10 and 11 discuss MIMO systems and space-time (ST) coding