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Journal ArticleDOI

An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

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TLDR
A novel orthogonal concatenated code and cyclic redundancy check have been used to mitigate the effects of data corruption in the user data and a novel memory management algorithm is proposed that helps to process the data at the back-end computing nodes removing the added path delays.
Abstract
Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

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Citations
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Journal ArticleDOI

Error detection and control of IIoT network based on CRC algorithm

TL;DR: The proposed CRC algorithm can reduce the error rate of the system by detecting and controlling the errors, and the validity of CRC algorithm is verified by experiments.
Journal Article

Fixed-latency system for high-speed serial transmission between FPGA devices with Forward Error Correction

TL;DR: The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length.
Journal ArticleDOI

Condition Assessment of Nuclear Power Plant Equipment Based on Machine Learning Methods: A Review

Yong Xu, +2 more
- 27 Feb 2023 - 
TL;DR: In this article , a detailed literature survey on state-of-the-art machine learning methods for NPP equipment condition assessment is presented, including major failure modes, data sources, maintenance strategies, and relationship between equipment lifetime, assessment technology, and maintenance strategy.
References
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Book

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Proceedings ArticleDOI

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

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Channel Coding Techniques for Wireless Communications

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Patent

FPGA configuration memory with built-in error correction mechanism

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Journal Article

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