Delft University of Technology
Analysis and Design of VCO-Based Phase-Domain ΣΔ Modulators
Sönmez, Uğur; Sebastiano, Fabio; Makinwa, Kofi A.A.
DOI
10.1109/TCSI.2016.2638827
Publication date
2017
Document Version
Accepted author manuscript
Published in
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Citation (APA)
Sönmez, U., Sebastiano, F., & Makinwa, K. A. A. (2017). Analysis and Design of VCO-Based Phase-
Domain ΣΔ Modulators.
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
,
64
(5), 1075-
1084. [7817814]. https://doi.org/10.1109/TCSI.2016.2638827
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1
Abstract— VCO-based phase-domain Σ
Δ modulators employ
the combination of a voltage-controlled-oscillator (VCO) and an
up/down counter to replace the analog loop filter used in
conventional ΣΔ modulators. Thanks to this highly digital
architecture, they can be quite compact, and are expected to
shrink even further with CMOS scaling. This paper describes the
analysis and design of such converters. Trade-offs between design
parameters and the impact of non-idealities, such as finite counter
length and VCO non-linearity, are assessed through both
theoretical analysis and behavioral simulations. The proposed
design methodology is applied to the design of a phase-to-digital
converter in a 40-nm CMOS process, which is used to digitize the
output of a thermal-diffusivity temperature sensor, achieving
±0.2° (3σ) phase inaccuracy from -40 to 125 °C and a sensor-
limited resolution of 57 m° (RMS) within a 500-Hz bandwidth.
Measurements on the prototype agree quite well with theoretical
predictions, thus demonstrating the validity of the proposed design
methodology.
Index Terms— VCO-based Sigma-Delta modulator, Time-to-
digital converter, Phase-to-digital converter, Quantization noise
I. I
NTRODUCTION
N recent years, time-to-digital converters (TDCs) have found
many applications, especially in digital PLLs and
instrumentation applications [1][2]. One specific class of TDCs,
known as phase-to-digital converters, can be used to digitize the
phase of a periodic input signal. Phase-to-digital converters
based on the ΣΔ ADC architecture, i.e. phase-domain ΣΔ
m
odulators (PD
ΣΔMs), have been used in readout circuits for
s
ingle-photon avalanche diodes (SPADs) [3], wireless receivers
[4], resistor-based temperature sensors [5], and thermal-
diffusivity-based (TD) temperature sensors [6].
Fig. 1 shows a simplified block diagram of a PDΣΔM. Here,
a
n input signal (V
IN
) at frequency F
IN
and with a phase shift Φ
IN
is multiplied by the clock signal V
DEM
, which is at the same
carrier frequency as V
IN
(F
DEM
= F
IN
). This results in a DC
component proportional to their phase difference, as well as
higher order components. The multiplier’s output is applied to
a loop filter, which in the case of a 1
st
-order modulator is an
integrator [7]. The loop filter drives an M bit quantizer, which,
This paper was submitted for review on 21
st
of June, 2016. This work was
supported in part by the Dutch Technology Foundation STW.
Ugur Sonmez is with Electronic Instrumentation Lab., part of Delft
University of Technology in Mekelweg 4, 2628CD Delft, The Netherlands (e-
mail: u.sonmez@tudelft.nl).
in turn, drives an M bit phase DAC that adjusts the phase of
V
DEM
. The loop attempts to minimize the DC component at the
integrator input in a
ΣΔ manner, and as a result, the output bit-
s
tream is a digital representation of the signal phase
Φ
IN
.
The architecture of a PDΣΔM is similar to that of an analog
P
LL, and as such it is capable of rejecting wide-band noise
while detecting the phase of an input signal relative to that of a
reference. This property has been exploited for the readout of
temperature sensors based on the thermal diffusivity (TD) of
silicon [6]-[8]. Such TD sensors output a small (millivolt-level)
signal, whose phase-shift is a function of temperature, but
which is accompanied by relatively large amounts of wide-band
noise. Since their accuracy improves with process scaling,
smart TD sensors, i.e. TD sensors with a digital output, are well
suited for the thermal management of SoCs. In such
applications, however, area is at a premium, and so most
published designs occupy less than 10,000 µm
2
[10][11]. This
in turn puts pressure on the area of the PD
ΣΔM, which currently
d
ominates the area of smart TD sensors.
This issue has been addressed by the adoption of a highly
digital PD
ΣΔM based on a voltage-controlled oscillator (VCO),
f
irst implemented in a mature 0.16-
μm CMOS process [8], and
l
ater shown to scale in a more advanced 40-nm CMOS process
[9]. Inspired by compact VCO-based ADCs [12][13], a VCO
translates the input signal into the frequency domain. The
phase-shift of this frequency-domain signal is then digitized by
an all-digital phase-domain ADC based on an up/down counter,
Fabio Sebastiano is with Delft University of Technology in Mekelweg 4,
2628CD Delft, The Netherlands (e-mail: f.sebastiano@tudelft.nl).
Kofi A. A. Makinwa is with Delft University of Technology in Mekelweg
4, 2628CD Delft, The Netherlands (e-mail: f.sebastiano@tudelft.nl).
Analysis and Design of VCO-Based
Phase-Domain ΣΔ Modulators
Uğur Sönmez, Member, IEEE, Fabio Sebastiano, Member, IEEE, and Kofi A. A. Makinwa, Fellow,
IEEE
I
Fig. 1. Block diagram of an analog PDΣΔM.
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSI.2016.2638827
Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
2
which acts as an integrator. Thanks to this highly digital
architecture, such VCO-based PD
ΣΔMs take full advantage of
t
echnology scaling, as proven by a x3 smaller area and x2 less
supply voltage requirement when ported from 0.16-μm to 40-
n
m CMOS [8][9]. However, an analysis of this architecture
discussing potential drawbacks and design trade-offs, has not
yet been reported.
This paper will analyze the unique features of VCO-based
PD
ΣΔMs that differentiate them from VCO-based ADCs and
a
nalog-based PD
ΣΔMs. Section II will describe the operation
o
f a general multi-bit VCO-based PD
ΣΔM. The quantization
e
rror associated with its digital counter is discussed in section
III. Section IV discusses the design of the digital counter, based
on counter wrap-around constraints. The effect of non-linearity
is tackled in section V. A second order modulator with
potentially higher SNR is presented in section VI. In section
VII, the developed models will be used to go through the design
procedure of a prototype first-order PD
ΣΔM and expected
p
erformance will be compared to experimental results. Finally,
the conclusions highlights how the proposed design procedure
can lead to area-efficient VCO-based PD
ΣΔMs with
p
erformance comparable to analog-based designs.
II. VCO-B
ASED
PDΣΔM
A
RCHITECTURE
The VCO-based version of this architecture is shown in Fig.
2(a). V
IN
is converted into variations of the VCO’s output
frequency. The counter acts like an integrator, while its up-
down input (DEM) facilitates chopper demodulation, i.e.
multiplication by a square wave, since it determines whether the
counter’s state is either incremented or decremented. The value
accumulated by the counter after one cycle of DEM
will then be
proportional to the integrated phase-shift between DEM and the
VCO’s output frequency, thus emulating the function of an
integrator.
This highly digital implementation avoids the need for the
large capacitors usually employed in analog loop filters and
enables an efficient implementation of the M bit quantizer,
which can be realized by sampling the M MSB’s of the digital
integrator output.
For maximum accuracy, both analog and VCO-based
modulators are usually operated as incremental converters, in
which the integrator is reset before each conversion [14]. A sinc
filter (implemented by a simple counter) can then be used to
decimate the converter’s output [14].An implementation of the
first order VCO-based PD
ΣΔM is shown in Fig. 2 (b). An S
bit
up/down counter is used to combine demodulation and
integration, while an M bit register acts as the quantizer. The
quantizer sampling clock (F
S
) is typically chosen at the same
frequency as F
DEM
[7].
In order to prevent meta-stability problems in the counter, a
flip-flop is used to synchronize the up/down signal to the next
edge of F
VCO
. This is similar to the clock re-synchronization
[15] required when two clock domains cross each other.
This
r
e-synchronization clock is shown as F
SYNC
in Fig. 2(b).
III. N
OISE
A
NALYSIS
A
ND
C
OUNTER
Q
UANTIZATION
The VCO-based PDΣΔM has three major noise sources: ΣΔ
q
uantization noise, up/down counter’s quantization error and
VCO’s phase noise. As is well-known, the ΣΔ’s quantization
n
oise can be reduced by increasing M, its order or sampling rate
[18].
The second noise source, due to up/down counter’s
q
uantization, is unique to VCO and counter based
ΣΔ
m
odulators. Unlike an analog integrator, an up/down counter
can only count integer values and hence imposes rounding on
its input. In the following, a simple expression for the
quantization noise associated with the operation of the up/down
counter will be derived.
For this analysis, we will model the counter as an ideal
discrete-time integrator that introduces some input-referred
quantization error at the end of every up/down cycle. The
timing diagram in Fig. 3 shows how this simplification can be
made. Here, we are also assuming that the input carrier signal
is a sinusoid with frequency F
IN
and a signal phase shift Φ
IN
with respect to the reference square-wave up/down signal with
Φ
DAC
= 0.
The frequency of the VCO (F
VCO
) can be expressed as:
(1)
where K
VCO
is the VCO gain, V
A
is the amplitude of the input
carrier and F
NOM
is the nominal VCO output frequency. After
integrating F
VCO
for each full up period (τ
UP
) and a full down
period (
τ
DOWN
), an ideal counter, i.e. a counter without any
quantization error, would compute the residual count C given
by:
(a)
F
VCO
V
IN
(Φ
IN
)
Pre-Set
S-Bit Up/Down
Counter
Up/Down
CLK
RESET
OUT
[S-1:0]
D Q D Q
FSYNC
D Q
FSYNC
2
M
Element Unary Phase DAC
Sel
F
SYNC
M-Bit
Register
Q
D
Bitstream
M
M
M-Bit MUX
D Q
FSYNC
F
IN
Front-End
& VCO
F
S
V
D
EM
(b)
Fig. 2. (a) Block diagram, and (b) circuit-level implementation of the VCO-
based PDΣΔM architecture.
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSI.2016.2638827
Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
3
!"#
(3)
Every period, C is computed and then accumulated with the
previous result. For an up/down signal with a duty cycle of 50%
(
τ
UP
= τ
DOWN
= 0.5/F
IN
), C becomes:
$%
(4)
It should be noted that while an exact 50% duty cycle can
be guaranteed by a fully digital chopper, the mismatch or duty-
cycle errors of an analog chopper will result in residual offset
[16]. The absence of residual chopper offset is a distinct
advantage of this architecture.
Shifting the phase of the up/down signal by
&
(due to
the phase DAC action) is equivalent to shifting the input signal
by -
&
; thus a more general form of (4) is:
$%
&
(5)
During regular ΣΔ operation, the feedback loop ensures that
o
n average sin(
Φ
IN
–Φ
DAC
) = 0. Since sin(Φ
IN
– Φ
DAC
) ≈ Φ
IN
–
Φ
DAC
for small phase differences, we can model the relationship
between C and phase as a gain factor K (Fig. 4). The phase-to-
count gain
can be readily defined from (5) as:
(6)
However, a digital counter can only accumulate integer
values because it only responds to the edges of F
VCO,
which is
equivalent to rounding C to an integer before the accumulation
operation. Fig. 5 demonstrates the timing diagram resulting
from such synchronization. With this additional
synchronization step, the quantization is in essence a “round
up” operation, where the counter is able to round up the
fractional count at its input before integration. The errors
ΔQ
U
(N) and ΔQ
D
(N) denote the fractional count error at the N
th
cycle in the up and down period, respectively, and as round-up
errors, they are bounded by [0 1] (Fig. 5).
ΔQ
U
(N) and ΔQ
D
(N) are deterministic for a given F
VCO
and
up/down signal. As will be shown later, VCO’s accumulated
jitter at the N
th
cycle will randomize the timing and duration of
events
ΔQ
U
(N) and ΔQ
D
(N). Thus, the VCO will introduce
significant dithering, and the quantization error can be assumed
to be uniformly and randomly distributed on the [0 1] interval
and uncorrelated in time.
This is analogous to approximating as white noise the
quantization error introduced by the comparator of a ΣΔ
m
odulator [17]. Noting that the average quantization error is
0.5, the variance of ΔQ
U
(N) and ΔQ
D
(N) can then be computed
as [18]:
'
(
)
*
+
,
-
)
.*
/
0
0
(7)
As can be seen on Fig. 5, the total error for the N
th
cycle
[
ΔQ
T
(N)] is given by the error on the up period minus the error
on the down period
1
2
3
4
5
1
2
6
4
1
2
&
4
7
5
1
2
&
4
1
2
6
4
0
1
2
6
4
1
2
&
4
1
2
6
4
0
(8)
The total error after N up/down cycles can be written as the sum
of the following series:
8
1
2
3
9
:
;
/
1
2
6
0
1
2
&
0
1
2
6
1
2
&
<
1
2
6
4
0
(9)
Since each element in the series has a variance of
'
(
)
, and is
assumed to be uncorrelated from the others, the variance of the
total error is equal to the sum of all component variances:
Fig. 3 Timing diagram demonstrating how up/down counting can be modeled
as a combination of chopping and discrete-time integration.
Fig. 4. Block diagram of the ideal discrete-time PDΣΔM with a discrete-time
integrator.
Fig. 5. Timing diagram demonstrating the error introduced by
metastability
synchronization of up/down signal to F
VCO
.
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSI.2016.2638827
Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
4
=
)
>
8
1
2
3
9
:
;
/
?
@
4
'
(
)
(10)
while the mean of the total error is zero. When N A 1, this error
c
onverges to 8N'
(
)
. The bandwidth of this error is F
IN
/2, since
it manifests every time an up/down count period is completed.
Using (7), we get the total power of the error in fractional counts
(
'
33B
)
) for a bandwidth F
BW
:
'
33B
)
C
D
EF
(11)
If the sampling rate (F
S
) of the PDΣΔM is chosen equal to
F
IN
, then the ratio F
S
/2F
BW
is also known as the oversampling
ratio (OSR) of the
ΣΔ modulator.
N
ow, we can replace the discrete-time block in Fig. 4 with
an integrator and an additive white noise source (ΔQ
ERR
) with a
power of
'
33B
)
, as shown in Fig. 6.
The error in fractional counts can be directly converted into
phase, which results in an input-referred phase error with an in-
band power of
'
G
)
, where:
'
G
)
D
H
IJK
H
)
(12)
By using (6), the RMS in-band error in radians (
'
GLM
) is:
=
N
L
O
$%
PQ%
R
0
S
IJK
H
(13)
Looking at (13), we can make an important conclusion: the
input-referred quantization noise due to the digital counter
scales inversely with the product of signal amplitude and VCO
gain, i.e. the frequency swing at the VCO output. For a given
F
IN
and V
A
, K
VCO
or OSR must be increased to suppress such
quantization noise. Since a larger OSR implies a lower
conversion speed, increasing K
VCO
is more desirable.
This analysis has been also confirmed by system-level
simulations, i.e. the simulation of an ideal
ΣΔ modulator with
a
dditive noise (to breakup strong idle tones) as shown in Fig. 6
(simulated in Matlab), and a mixed-signal simulation in
CppSim [19].
In both models, K
VCO
V
A
= 70 MHz, F
IN
= F
S
= 1.17 MHz,
F
NOM
= 600 MHz, S = 8 and M = 3. The phase DAC spans
78.75° with steps of 11.25°. A block diagram of the mixed-
signal CppSim model is shown in Fig. 7. A high-frequency
clock (F
SYNC
) is used to generate the 3-bit phase DAC values
ranging from 11.25° to 90°. The up/down counter was compiled
as a Verilog block, and is hence ideal. Standard D flip-flop,
VCO and multiplexer elements were used from CppSim’s
standard libraries.
Fig. 8 shows the power spectral density (PSD) simulated in
the two models together with the quantization noise floor
calculated from (13) (dashed blue line). Good agreement is
achieved at low frequencies between both models and the
theoretical prediction. The quantization noise is predicted to be
38 m° for OSR = 1024, which corresponds to ~1 ms conversion
time.
The idle tone around 400 kHz for the CppSim model
r
esults is attributed to the limited accuracy of the time-domain
model (100 ps). The idle tone is not observed in measurement
results. Although low-frequency idle tones are a typical issue
for 1
st
-order modulator, they do not appear in the simulation
shown in Fig. 8 because of the dithering action of the thermal
noise superimposed on the input signal. In typical sensing
applications of the phase-domain read-out, such as those shown
in section VII, the input signal is characterized by a small
amplitude and relatively large noise that is enough to dither the
modulator.
The agreement of the two models with (13) means that long
time-domain simulations can be avoided when only the in-band
behavior of the counter’s quantization noise is of interest, since
Fig. 6. Block diagram of the PDΣΔM with white additive noise source
modelling
the counter quantization noise.
Fig. 7. Block diagram of the implemented CppSim model.
Fig. 8. Power spectral density of the output bitstream of an ideal Σ
Δ model
with additive noise and of a transient simulation.
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSI.2016.2638827
Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
