Journal ArticleDOI
Comparison of the scaling characteristics of nanoscale silicon N-channel multiple-gate MOSFETs
A. Breed,K.P. Roenker +1 more
- Vol. 56, Iss: 1, pp 135-141
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In this article, the scaling characteristics of the three leading multi-gate MOSFET designs, namely finFET, trigate and omega-gate, were compared using a commercial numerical device simulator.Abstract:
This paper compares the scaling characteristics of the three leading multi-gate MOSFET designs, namely the finFET, trigate and omega-gate. A commercial numerical device simulator is employed using a common set of material parameters, device physics models and performance metrics. Examined initially are the short channel effects including the subthreshold slope S and drain induced barrier lowering DIBL as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin body's width and height, the oxide thickness and the channel doping. The results suggest that the omega-gate MOSFET shows the best device scaling characteristicsread more
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Journal ArticleDOI
SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey
Pavankumar Bikki,P. Karuppanan +1 more
TL;DR: In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed and a classification of these approaches made based on their key design and functions is made.
Journal ArticleDOI
Negative Resistance Region 10 nm Gate Length on FINFET
TL;DR: In this article, the physical characteristics of fin-field effect transistor (fin-effect transistor) behavior were investigated and a semi-classical electron transfer method was used based on drift diffusion approximation by TCAD (Tiber CAD) software.
Journal ArticleDOI
A comparative study on electrothermal characteristics of nanoscale multiple gate MOSFETs
TL;DR: The electrothermal characterization of three-type nanoscale MG MOSFETs, i.e., Π-gate, quadruple-gate (QG), and Ω-gate MOSfETs is presented, and the transient temperature response of MG MosFets to different waveforms are captured and compared.
Journal Article
TCAD Simulation Analysis of Tri-Gate SOI FINFET and Its Application
Isha Padiyar,D.S Gangwar +1 more
TL;DR: In this article, the performance analysis of tri-gate (TG) silicon-on-insulator (SOI) FinFET using TCAD simulation is presented, where various simulations are performed on the process parameters like Fin width, Fin height and Underlap to determine the behavior of proposed structure in terms of leakage current, drive current and DIBL.
References
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Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High performance fully-depleted tri-gate CMOS transistors
Brian S. Doyle,Suman Datta,Mark Beaverton Doczy,Scott Hareland,B. Jin,Jack Portland Kavalieros,Thomas D. Linton,Anand Portland Murthy,Rafael Rios,R. Chau +9 more
TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Pi-Gate SOI MOSFET
TL;DR: In this paper, the concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, the proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFLET.