Journal ArticleDOI
Current sensing differential logic: a CMOS logic for high reliability and flexibility
TLDR
This CSDL eliminates the timing constraints between the enable signal and input signals, which cause difficulties in design with conventional differential logic families, by employing a simple clocking scheme.Abstract:
In this paper, we present a highly reliable and flexible CMOS differential logic called current sensing differential logic (CSDL). This CSDL eliminates the timing constraints between the enable signal and input signals, which cause difficulties in design with conventional differential logic families, by employing a simple clocking scheme. The power-delay product of CSDL is also reduced by using a swing suppression technique. To verify the reliability and the applicability of the proposed CSDL in large very large-scale-integration systems, a 64-bit carry-lookahead adder has been fabricated in a 0.6 /spl mu/m CMOS technology. Experimental results show that the critical path delay is 3.5 ns with a power consumption of 27 mW at 50 MHz.read more
Citations
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Proceedings ArticleDOI
A low voltage to high voltage level shifter circuit for MEMS application
TL;DR: In this article, a low voltage to high voltage converter circuit was proposed to solve the high voltage swing problem in a 0.35 SOI process, where all the low voltage devices were removed.
Book ChapterDOI
Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL)
S.B. Tatapudi,Valeriu Beiu +1 more
TL;DR: After a short review of the state-of-the-art, a new low-power differential threshold logic gate is introduced: split-precharge differential noiseimmune threshold logic (SPD-NTL), based on combining the split-level precharge differential logic with a technique for enhancing the noise immunity of threshold logic gates: noise suppression logic.
Journal ArticleDOI
High-Voltage CMOS Controller for Microfluidics
TL;DR: This integrated circuit represents an advancement in microfluidic technology when used in conjunction with a charge coupling device (CCD)-based optical system and a glass micro fluidic channel, enabling a portable and cost-efficient platform for genetic analysis.
Journal ArticleDOI
Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic
TL;DR: Experimental results show that the performance of the SPDL is about two times as good as that of the previous half-rail differential logic (HRDL) in terms of power-delay product and has stable operation under mismatch or parameter variation.
Proceedings ArticleDOI
A charge recycling differential noise immune perceptron
TL;DR: In this paper, the authors propose a method to solve the problem of Abs.1.5.0-1/3/3.0/2/1/2.0
References
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Proceedings ArticleDOI
Cascode voltage switch logic: A differential CMOS logic family
TL;DR: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described.
Book
Low-Power Digital VLSI Design: Circuits and Systems
TL;DR: This paper presents a methodology for designing low-Voltage Low-Power VLSI CMOS Circuit Design that addresses the challenge of integrating low-voltage components into a coherent system.
Journal ArticleDOI
Design procedures for differential cascode voltage switch circuits
K.M. Chu,D.L. Pulfrey +1 more
TL;DR: Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented and are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions.
Journal ArticleDOI
Differential current switch logic: a low power DCVS logic family
Dinesh Somasekhar,Kaushik Roy +1 more
TL;DR: Differential current switch logic (DCSL) as mentioned in this paper is a new logic family for implementing clocked CMOS circuits, which achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree.
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