Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Kohei Miyase,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Yuta Yamato,Hiroshi Furukawa,Xiaoqing Wen,Seiji Kajihara +8 more
- pp 52-58
TLDR
A novel test relaxation method, called Distribution-Controlling X-Identification (DC-XID), which controls the distribution of X-bits identified from a set of fully-specified test vectors for the purpose of effectively reducing IR-drop is proposed.Abstract:
Test data modification based on test relaxation and X-filling is the preferable approach for reducing excessive IR-drop in at-speed scan testing to avoid test-induced yield loss. However, none of the existing test relaxation methods can control the distribution of identified donpsilat care bits (X-bits), thus adversely affecting the effectiveness of IR-drop reduction. In this paper, we propose a novel test relaxation method, called Distribution-Controlling X-Identification (DC-XID), which controls the distribution of X-bits identified from a set of fully-specified test vectors for the purpose of effectively reducing IR-drop. Experimental results on large industrial circuits demonstrate the effectiveness and practicality of the proposed method in reducing IR-drop, without any impact on fault coverage, test data volume, or test circuit size.read more
Citations
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A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment
Kohei Miyase,Yuta Yamato,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Xiaoqing Wen,Seiji Kajihara +7 more
TL;DR: This paper proposes a novel and practical CA (Compression-Aware) test modification scheme for reducing IR-drop in the widely-used broadcast-scan based test compression environment and can achieve significant IR- drop reduction even when a test cube only has a small number of X-bits.
References
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
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VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Proceedings ArticleDOI
Minimizing power consumption in scan testing: pattern generation and DFT techniques
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.