Journal ArticleDOI
Effects of gate-last and gate-first process on deep submicron inversion-mode InGaAs n-channel metal-oxide-semiconductor field effect transistors
TLDR
In this paper, the thermal budget of gate-last and gate-first process for deep-submicron self-aligned InGaAs MOSFETs was investigated, and the authors concluded that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate first process.Abstract:
Recently, encouraging progress has been made on surface-channel inversion-mode In-rich InGaAs NMOSFETs with superior drive current, high transconductance and minuscule gate leakage, using atomic layer deposited (ALD) high-k dielectrics. Although gate-last process is favorable for high-k/III–V integration, high-speed logic devices require a self-aligned gate-first process for reducing the parasitic resistance and overlap capacitance. On the other hand, a gate-first process usually requires higher thermal budget and may degrade the III–V device performance. In this paper, we systematically investigate the thermal budget of gate-last and gate-first process for deep-submicron InGaAs MOSFETs. We conclude that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate-first process. We thus report on the detailed study of scaling metrics of deep-submicron self-aligned InGa...read more
Citations
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Journal ArticleDOI
Channel Length Scaling of MoS2 MOSFETs
Han Liu,Adam T. Neal,Peide D. Ye +2 more
TL;DR: The performance limit of short channel MoS(2) transistors is dominated by the large contact resistance from the Schottky barrier between Ni and MoS (2) interface, where a fully transparent contact is needed to achieve a high-performance short channel device.
Proceedings ArticleDOI
First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach
TL;DR: The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In 0.53 Ga 0.47 as mentioned in this paper.
Journal ArticleDOI
Effects of (NH4)2S passivation on the off-state performance of 3-dimensional InGaAs metal-oxide-semiconductor field-effect transistors
TL;DR: In this paper, the effect of (NH4)2 S passivation with different concentrations (20, 10, or 5%) on the off-state performance of 3D MOSFETs has been systematically studied.
Journal ArticleDOI
III-V-on-nothing metal-oxide-semiconductor field-effect transistors enabled by top-down nanowire release process: Experiment and simulation
TL;DR: In this article, a hydrochloric acid-based release process has been developed to create an air gap beneath the InGaAs channel layer, forming the nanowire channel with width down to 40 nm.
Journal ArticleDOI
GaSb Metal-Oxide-Semiconductor Capacitors with Atomic-Layer-Deposited HfAlO as Gate Dielectric
TL;DR: In this article, an interface characterization of p-type GaSb metal-oxide-semiconductor (MOS) structures has been performed with Al-first and Hf-first HfAlO gate dielectrics deposited via atomic layer deposition.
References
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Journal ArticleDOI
High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm
Yi Xuan,Yanqing Wu,Peide D. Ye +2 more
TL;DR: In this article, a 0.4mum gate-length MOSFET with an Al2O3 gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10-6 A/cm2 at 4.0 V.
Journal ArticleDOI
GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition
Peide D. Ye,G. D. Wilk,J. Kwo,B. Yang,H.-J.L. Gossmann,M.R. Frei,S.N.G. Chu,Joseph Petrus Mannaerts,M. Sergent,Minghwei Hong,K.K. Ng,J. Bude +11 more
TL;DR: In this article, the gate dielectric grown by atomic layer deposition (ALD) was demonstrated for the first time on a III-V compound semiconductor MOSFET.
Journal ArticleDOI
Enhancement-Mode GaAs MOSFETs With an $\hbox{In}_{0.3} \hbox{Ga}_{0.7}\hbox{As}$ Channel, a Mobility of Over 5000 $ \hbox{cm}^{2}/\hbox{V} \cdot \hbox{s}$ , and Transconductance of Over 475 $\mu\hbox{S}/\mu\hbox{m}$
Hill Richard J,David A. J. Moran,Xu Li,Haiping Zhou,Douglas Macintyre,Stephen Thoms,Asen Asenov,P. Zurcher,K. Rajagopalan,Jonathan K. Abrokwah,Ravindranath Droopad,Matthias Passlack,I.G. Thayne +12 more
TL;DR: In this article, the authors presented a metal-gate high-k-dielectric enhancement-mode (e-mode) III-V MOSFET with the highest reported effective mobility and transconductance to date.
Journal ArticleDOI
Ga 2 O 3 (Gd 2 O 3 )/InGaAs enhancement-mode n-channel MOSFETs
Fan Ren,J. M. Kuo,Minghwei Hong,W. S. Hobson,James Robert Lothian,Jenshan Lin,H.S. Tsai,Joseph Petrus Mannaerts,J. Kwo,S.N.G. Chu,Young-Kai Chen,A.Y. Cho +11 more
TL;DR: In this article, the first Ga/sub 2/O/sub 3/(Gd/sub Gd/Sub O/Sub 3)/Gd sub 2.5/Gd 2.O/Sub 2.
Journal ArticleDOI
High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3∕Ga2O3(Gd2O3) as gate dielectrics
TL;DR: In this paper, a self-aligned inversion-channel In0.53Ga0.47 MOSFET with gate dielectric of Al2O3(2nmthick)∕GGO(5 nmthick), a maximum drain current of 1.05A∕mm, a transconductance of 714mS∕m, and a peak mobility of 1300cm2∕Vs have been achieved, the highest ever reported for III-V inversion channel devices of 1μm gate length.
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High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm
Yi Xuan,Yanqing Wu,Peide D. Ye +2 more