The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of ...

http://ieeexplore.ieee.org/iel5/5/31324/01456901.pdf

Highly Linear Mixer for On-chip RF Test in 130 nm CMOS

Microelectronic circuits

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

In this paper, fundamental performance limits and scaling of a double-balanced passive mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, LG. We analyze the performance in terms of conversion gain (GC), 1-dB compression point (P1-dB) which we derive, and SSB Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and modeling results for mixers designed in CMOS 350 nm to 32 nm technology. We introduce a mixerpsilas figure-of-merit (FOMMIXER) to compare performance with technology scaling. Circuit designers and system architects can use this paper to find a suitable process technology that will meet their specifications.

Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

Traditionally the front-end of a transmitter for cable television designed for the DOCSIS standard consists of a combination of multiple DACs and analog mixers. In this traditional transmitter architecture, in each front-end a single carrier is converted in a DAC and upconverted to the desired RF frequency. This research work analyzes and realizes a new approach of replacing this analog front-end in the transmitter by digital signal processing that upsamples, combines and upconverts the carriers, followed by a single DAC that generates the RF signal without further upconversion. The new approach has the advantage that the complexity of a multi-carrier transmitter is reduced, because less analog components are required which require tuning and calibration. Chapter 2 presents the communication system and the challenges when many channels are combined. A theoretical study about the consequences of the combining of multiple channels in the digital domain on the properties of the signal that is converted with the DAC is given and the optimal level for amplitude clipping in the case of a limited number of carriers and in the case of many carriers is analyzed. Chapter 3 introduces the DOCSIS broadcast system and the RF requirements that are specified in the standard. From this standard the requirements on a single transmitter that is capable to transmit multiple channels is derived. Chapter 4 studies the traditional DAC/mixer combination and the requirements for the individual components that are needed and from these specifications the power consumption of such a transmitter is estimated and is used to compare against the proposed method. Using such an architecture the minimum power consumption is estimated to be about 1.2W per channel that is being broadcasted. In Chapter 5 the advantages of increasing the digitization and of advanced CMOS technologies are explained. The new approach of combining the carriers in the digital signal processing is analyzed and requirements for the digital signal processing functions are set. The number of carriers that can be transmitted using a single ’all-digital’ transmitter increases significantly, compared to the traditional analog dual conversion transmitter, because the complexity of the analog core of the ’all-digital’ transmitter is independent of the number of channels. The ’all-digital’ transmitter can broadcast all channels that could be present in the full DOCSIS band with a single DAC. The main limitation in the number of channels is the limit in power dissipation that can be handled by the package, since adding more channels does only affect the digital signal processing and does not increase the complexity in the analog domain. Chapter 6 proposes the implemented ’all-digital’ transmitter architecture. Of this architecture the requirements for the building blocks are studied and the power consumption of these digital circuits is estimated. In Chapter 7 the digital-to-analog converter used in this ’All-digital’ transmitter is analyzed and several models are derived to estimate the performance of the DAC in case of imperfections. A new framework is given for modeling and analysis of current steering DAC performance in the case of broadband signals, and especially at high sample rates. For such broadband signals, error mechanisms that create distortion around the mid-scale transitions are more dominant in the performance of the system than error mechanisms that create distortion at the extremes of the amplitude range. Using fully binary DACs or DACs with a low segmentation results in a higher distortion for signals that have wideband properties than for narrowband signals. When the DAC performance is affected by output conductance, a higher output conductance is allowed to achieve a similar performance for wideband signals than for a narrowband signal. Using these models an architecture for the DAC is selected and the measurement results of the realized DAC are shown. In Chapter 8 the IC implementations are being discussed. The transmitter concepts have been used in a rationalized manner to design and implement a 12-bit 2.8GS/s DAC in combination with digital signal processing that upsamples, combines and upconverts the carriers in a 90nm CMOS process, which serves as a vehicle IC to verify the validity of the ’all-digital’ transmitter concepts proposed in this thesis. Based on this DAC, three different versions of a complete ’all-digital’ transmitter, which consist of a combination of the digital signal processing and a DAC, were designed and implemented as ICs. The first two versions, the second being a redesigned version of the first one, use current mode logic for the digital signal processing, which is optimized to be able to run at the desired sample frequency of 2.8GS/s. Since the digital signal processing is made in current mode logic and synchronous with the DAC clock, no interference is observed. The third version uses static CMOS logic in combination with several methods, such as the use of poly-clock phases, to reduce the interference from the digital signal processing to the sensitive analog circuits. It is shown that the combination of these techniques to reduce the interference is sufficient to achieve the required performance. The preferred logic style to implement the digital circuits is standard CMOS logic, which is efficient in terms of power consumption and effort to implement the digital circuits. The proposed multi-carrier transmitter architecture is compared against the traditional multi-carrier transmitter. It has been shown that the proposed multi-carrier DOCSIS transmitter can be more power and area efficient when multiple channels are being broadcasted than multiple traditional DOCSIS transmitters that have their outputs combined. In the case of 64 channels the expected reduction in the power consumption is more than 90%.

background

/pdf/multi-carrier-single-dac-transmitter-approach-applied-to-5ewofl0dgt.pdf

Multi-carrier single-DAC transmitter approach applied to digital cable television

In this thesis work, a highly linear passive attenuator and mixer were designed to be used in a wide-band Transmission Observation Receiver (TOR). The TOR is a low IF receiver that accepts RF frequencies from 2GHz to 7GHz, and produces corresponding IF bandwidths of 280MHz to 990MHz respectively, using low side LO injection. The dynamic range is maximized by using passive topologies for both the attenuator and the mixer. The system is dealing with different power levels ranging from -30dBm to +1dBm, and hence, a programmable digital step attenuator is used to attenuate large signals. It provides a maximum of 31dB of attenuation in 1dB steps. Different mixer architectures were compared, including CMOS mixer, mixer with dummy switches and quadrature mixer. Also, the performance of the mixer in both voltage mode and current mode was investigated. A double balanced passive mixer in voltage mode, with dummy switches was adopted in the final system since it proved to be the best in terms of meeting the requirements. The work was carried out in Ericsson in Lund, using Cadence, 65nm process. The circuit is true differential and it uses a supply voltage of 1.2V. The final results show a spurious free dynamic range of higher than 85dBc, minimum in band IIP3 of +15dBm , maximum IIP3 of +50dBm and a worst input return loss of less than -10dB. The amplitude and phase precision over the observation bandwidth were quite good, a worst phase error of less than 3 degrees was recorded and an amplitude error of 0.5dB. (Less)

https://lup.lub.lu.se/student-papers/record/8880246/file/8880249.pdf

Highly linear attenuator and mixer for wide band TOR in CMOS

/pdf/highly-linear-mixer-for-on-chip-rf-test-in-130-nm-cmos-2jsozggf29.pdf

The paper addresses on-chip test for IC RF transceivers. The baseband DSP available on chip serves as a tester while the RF front-end is reconfigured for test. The basic test setup is a loopback, enabled by a test attenuator and in some cases by an offset mixer, too. Different variants of this setup adopt the bypassing technique to boost testability. The existing limitations and tradeoffs in terms of test feasibility, controllability and observability versus the chip performance are discussed. The fault-oriented approach and the sensitization techniques are emphasized vs the functional test. The impact of production tolerances is addressed in terms of the detectability thresholds.

http://www.wseas.us/e-library/conferences/2006cscc/papers/534-386.pdf

Highly Linear Mixer for On-chip RF Test in 130 nm CMOS

Citations

Microelectronic circuits

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

Multi-carrier single-DAC transmitter approach applied to digital cable television

Highly linear attenuator and mixer for wide band TOR in CMOS

References

RF on-chip test by reconfiguration technique

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