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Open AccessJournal ArticleDOI

Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence

TLDR
A fast calculation tool for state-dependent capacitance of power distribution network achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation.
Abstract
A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.

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Book ChapterDOI

Solitary Electromagnetic Waves Generated by the Switching Mode Circuit

TL;DR: The solitary electromagnetic wave (SEMW) theory and the technologies of the low impedance lossy line (LILL) and the matched impedance lossY line (MILL) were successfully developed and are presented below together with the result of the analysis, experiments, and the review of the conventional theory and engineering.
Journal ArticleDOI

State-Dependence of On-Chip Power Distribution Network Capacitance

TL;DR: A state-dependent PDNcapacitance model that explains measurement results will be also proposed, composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate that reflects the changes of electrode potentials.
References
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Proceedings ArticleDOI

Combinational profiles of sequential benchmark circuits

TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Journal ArticleDOI

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

TL;DR: In this article, the dependence of the Vdd-Vss admittance on the different states of the circuit, the supply voltage, and the interconnect was investigated and the computation of the total supply current with ground bounce was performed.
Journal ArticleDOI

Linear Equivalent Circuit and Current Source for I/O (LECCS-I/O) Modeling of IC Power Current for EMI Simulation

TL;DR: In this article, the linear equivalent circuit and current source for I/O (LECCS-I/O) model was proposed to predict peak and valley frequencies of the power current spectra within an error of 2.5dB.
Proceedings ArticleDOI

Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits

TL;DR: This input vector can be used to enhance the on-chip decoupling capacitance in the standby mode and when the macroblock is not used or disabled by certain applications.
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