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Journal ArticleDOI

Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory

TLDR
In this article, a methodology to perform process variation-aware device and circuit design using fully physics-based simulations within limited computational resources, without developing a compact model, was proposed.
Abstract
We propose a methodology to perform process variation-aware device and circuit design using fully physics-based simulations within limited computational resources, without developing a compact model. Machine learning (ML), specifically a support vector regression (SVR) model, has been used. The SVR model has been trained using a dataset of devices simulated a priori, and the accuracy of prediction by the trained SVR model has been demonstrated. To produce a switching time distribution from the trained ML model, we only had to generate the dataset to train and validate the model, which needed ∼500 hours of computation. On the other hand, if 106 samples were to be simulated using the same computation resources to generate a switching time distribution from micromagnetic simulations, it would have taken ∼250 days. Spin-transfer-torque random access memory (STTRAM) has been used to demonstrate the method. However, different physical systems may be considered, different ML models can be used for different physical systems and/or different device parameter sets, and similar ends could be achieved by training the ML model using measured device data.

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Citations
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Journal ArticleDOI

MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET

TL;DR: In this paper, a post-CMOS magneto-electric FET (MEFET) is proposed for high-speed and low-power design in both logic and memory applications.
Journal ArticleDOI

Impact of Reference-Layer Stray Field on the Write-Error Rate of Perpendicular Spin-Transfer-Torque Random-Access Memory

TL;DR: In this article , a finite-temperature micromagnetic study of magnetization switching and write-error rates in a perpendicular magnetic tunnel junction with and without synthetic antiferromagnetic layer (SAF) is presented.
References
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Proceedings ArticleDOI

Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic

TL;DR: The manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform is demonstrated by achieving stable functionality and robust package level reliability and read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology.
Proceedings ArticleDOI

Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories

TL;DR: Major breakthroughs in MTJ design for STT-MRAM applications allowing reliable write for pulse lengths down to 1.5ns, data retention up to 125°C for 10 years and full compatibility with BEOL process up to 400°Cfor 1 hour are presented.
Journal ArticleDOI

Compact Modeling of Perpendicular-Magnetic-Anisotropy Double-Barrier Magnetic Tunnel Junction With Enhanced Thermal Stability Recording Structure

TL;DR: In this article, a physics-based compact model of Ta/CoFeB/MgO double-barrier magnetic tunnel junction (DMTJ) with enhanced thermal stability recording structure is presented.
Journal ArticleDOI

High-temperature thermal stability driven by magnetization dilution in CoFeB free layers for spin-transfer-torque magnetic random access memory

TL;DR: CoFeB free layers diluted with state-of-the-art non-magnetic metallic impurities are reported on, demonstrating that the magnetization is the primary factor driving the temperature dependence of the anisotropy and thermal stability of STT-MRAM devices.
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