Patent
Multiple well transistor circuits having forward body bias
TLDR
In this article, a semiconductor circuit includes a substrate and a first well formed in the substrate, where a first group of field effect transistors is formed and has a first body.Abstract:
In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.read more
Citations
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References
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Book
Solid state electronic devices
TL;DR: The Solid State Electronic Devices (SSED) as discussed by the authors is an introductory book on semiconductor materials, physics, devices, and technology, which aims to: 1) develop basic semiconductor physics concepts, and 2) provide a sound understanding of current semiconductor devices and technology.
Journal ArticleDOI
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Journal ArticleDOI
A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
Tadahiro Kuroda,T. Fujita,Shinji Mita,Tetsu Nagamatsu,S. Yoshioka,Kojiro Suzuki,F. Sano,M. Norishima,M. Murota,M. Kako,M. Kinugawa,Masakazu Kakumu,Takayasu Sakurai +12 more
TL;DR: This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 09 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT.
Proceedings ArticleDOI
A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation
TL;DR: In this paper, a dynamic threshold voltage MOSFET (DTMOS) was proposed to extend the lower bound of power supply to ultra-low voltages (06 V and below).
Journal ArticleDOI
Variable supply-voltage scheme for low-power high-speed CMOS digital design
Tadahiro Kuroda,Kojiro Suzuki,Shinji Mita,T. Fujita,F. Yamane,F. Sano,A. Chiba,Yohji Watanabe,K. Matsuda,T. Maeda,Takayasu Sakurai,Tohru Furuyama +11 more
TL;DR: In this paper, a variable supplyvoltage (VS) scheme was proposed to automatically generate minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency.