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Journal ArticleDOI

Series resistance of self-aligned silicided source/drain structure

TLDR
In this paper, the external resistance of the self-aligned silicided source/drain structure is examined by two-dimensional simulation considering recession of the contact interface due to the consumption of silicon during the silicidation process.
Abstract
The external resistance of the self-aligned silicided source/drain structure is examined by two-dimensional simulation considering recession of the contact interface due to the consumption of silicon during the silicidation process. It is observed that the recessed contact interface forces a significant amount of current to flow into the high-resistivity part of the junction, resulting in an increase of resistance as large as several hundred ohms-micrometers in comparison with the surface contact structure. The increase scales up with the scaledown of the minimum feature size, and the expected benefits of the salicide structure diminish for the sub-half-micrometer devices. A simple analytical explanation is proposed. By considering the recession of the contact interface, the reported high external resistance of short-channel MOSFETs is explained. Different source/drain contact types are compared, and it is concluded that the conventional salicide process should be modified for sub-half-micrometer devices. >

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Citations
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Journal ArticleDOI

Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation

TL;DR: In this paper, an advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime.

Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part I:

TL;DR: In this article, an advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime.
Journal ArticleDOI

Metal silicides: active elements of ULSI contacts

TL;DR: In this paper, the effect of suicide materials and formation processes on suicide stability, junction consumption, the ability to accurately profile shallow junctions, and contact resistance in series with the channel is discussed.
Journal ArticleDOI

The impact of active layer thickness on low-frequency noise characteristics in InZnO thin-film transistors with high mobility

TL;DR: In this paper, lowfrequency noise (LFN) characteristics in passivated InZnO thin-film transistors with various active layer thicknesses are matched to the mobility fluctuation model.
Journal ArticleDOI

DIBL considerations of extended drain structure for 0.1 /spl mu/m MOSFET's

TL;DR: In this article, the drain-induced-barrier-lowering (DIBL) considerations of the extended drain structure were studied using two-dimensional (2D) device simulations in the tenth-micrometer regime.
References
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Journal ArticleDOI

Models for contacts to planar devices

TL;DR: In this article, two basic models for rectangular contacts to planar devices, the Kennedy-Murley Model (KMM) and the Transmission Line Model (TLM), are discussed and compared.
Journal ArticleDOI

Comparison of transformation to low-resistivity phase and agglomeration of TiSi/sub 2/ and CoSi/sub 2/

TL;DR: In this paper, the phase transformation and stability of TiSi/sub 2/ on n/sup +/ diffusions were investigated and it was shown that more C49 and C54 nucleation events are required to completely transform narrow lines.
Journal ArticleDOI

Boron, fluorine, and carrier profiles for B and BF2 implants into crystalline and amorphous Si

TL;DR: In this paper, the authors used secondary ion mass spectrometry (SIMS) and carrier profiles, measured by differential capacitancevoltage (C‐V) profiling, of boron and fluorine implanted as B, F, BF, or BF2 ions into random and channeling orientations of crystalline silicon, and into silicon amorphized by silicon ion implantation.
Journal ArticleDOI

Analysis of the gate-voltage-dependent series resistance of MOSFET's

TL;DR: In this article, the intrinsic parasitic series resistance that occurs near the channel end of a MOSFET is analyzed, including the effects due to the unavoidable doping gradient near the metallurgical junction.
Journal ArticleDOI

The impact of intrinsic series resistance on MOSFET scaling

TL;DR: In this paper, the intrinsic parasitic series resistance associated with the practical structure of a MOSFET was examined, down to a channel length of 0.15 µm, and it was shown that the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered.
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