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Proceedings ArticleDOI

Simple and fast method of on-board decoupling capacitor selection and placement

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TLDR
Simple and fast method of on-board decoupling capacitor(decap) selection and placement is introduced, which can be performed easily based on math tools or general EDA tools and can both simplify the process and achieve good results when finding the optimal solution.
Abstract: 
Simple and fast method of on-board decoupling capacitor(decap) selection and placement is introduced, which can be performed easily based on math tools or general EDA tools This method is based on simple estimation formula of decap models, and can decide whether specific area needs some decaps or not, and what are the values It can both simplify the process and achieve good results when finding the optimal solution To perform this method, first, prepare the power network S parameters of PCB; second, set up the optimization topology, variables and goals; then perform the optimization by some optimizer; finally, we will get the suggested selection and placement scheme of decaps with the optimal impedance profile Detailed applications of one example case demonstrate the proposed method with reasonable goals achieved

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Citations
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Proceedings ArticleDOI

Reinforcement Learning-Based Optimal on-Board Decoupling Capacitor Design Method

TL;DR: The proposed reinforcement learning-based optimal on-board decoupling capacitor (decap) design method has successfully provided 37 optimal decap designs with 4 decaps assigned each and satisfied the required target impedance while minimizing the number of assigned decaps.
Proceedings ArticleDOI

Decoupling Capacitor Selection Algorithm for PDN Based on Deep Reinforcement Learning

TL;DR: An inductance-based method is utilized to calculate the port priority fist, and afterwards deep reinforcement learning (DRL) with deep neural network (DNN) is applied to optimize the assignment of decaps on the prioritized locations.
Proceedings ArticleDOI

Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm

TL;DR: In this paper, a practical case study is presented, where, in order to design an efficient PDN, the cumulative impedance of the PDN is optimized below the target impedance.
Journal ArticleDOI

Decoupling Capacitors Placement at Board Level Adopting a Nature-Inspired Algorithm

TL;DR: The capacitance value and the location of three decoupling capacitors are optimized in order to obtain an input impedance below a specific mask, by using a nature-inspired algorithm, the genetic one, in combination with two electromagnetic solvers used to compute the objective function.
Journal ArticleDOI

Efficient Iterative Process Based on an Improved Genetic Algorithm for Decoupling Capacitor Placement at Board Level

TL;DR: In this paper, a genetic algorithm is used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values.
References
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Journal ArticleDOI

Decoupling capacitor effects on switching noise

TL;DR: In this paper, the decoupling capacitor efficiency in reducing the power supply differential switching noise of the multichip-module (MCM) package structure employed in the IBM ES/9000 system is described.
Proceedings ArticleDOI

Decoupling capacitor effects on switching noise

TL;DR: In this article, the decoupling capacitor efficiency in reducing the power supply differential switching noise of the multichip-module (MCM) package structure employed in the IBM ES/9000 system is described.
Proceedings ArticleDOI

Advanced decoupling using ceramic MLC capacitors

TL;DR: In this article, the authors present a broad awareness that might reduce repetition and introduce a possible solution to the decoupling problem, noting that recent developments in high-speed decouplings have been in multiple simultaneous directions.
Journal ArticleDOI

Decoupling capacitors selection algorithm based on maximum anti-resonance points and quality factor of capacitor

TL;DR: In this paper, a decoupling capacitors selection algorithm based on maximum anti-resonance points of the power distribution network and the quality factor (Q) of the capacitor is proposed.
Proceedings ArticleDOI

Efficient multi-node optimal placement for decoupling capacitors on PCB

TL;DR: In this paper, an optimal combination of the decoupling capacitors is presented within a single port region to achieve the desired power integrity, and the optimal result is then applied to all port regions to achieve a better PDN design with lower impedance.
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