Patent
Strained silicon fin field effect transistor
Reads0
Chats0
TLDR
In this paper, the SiGe embedded body on a SOI substrate was used to form a novel FinFET, where the mobility in the Si channel was enhanced due to strain of the Si channels.Abstract:
Strained Si surrounding the SiGe embedded body on a SOI (silicon on insulator) substrate forms a novel FinFET. The mobility in the channel is enhanced due to strain of the Si channel. The strained Si FinFET includes a SOI substrate, an SiGe embedded body, a strained Si channel surrounding layer, an oxide layer, a poly Si gate electrode (or metal gate electrode), a source and a drain.read more
Citations
More filters
Patent
Semiconductor device, and manufacturing method thereof
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Patent
Tri-gate devices and methods of fabrication
TL;DR: In this paper, a gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the SINR, which is a semiconductor device consisting of a top surface and laterally-opposite sidewalls formed on a substrate.
Patent
Nonplanar transistors with metal gate electrodes
TL;DR: In this paper, a gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the SINR, and a pair of source and drain regions are then formed on opposite sides of the gate electrode.
Patent
Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication
Anthony J. Lochtefeld,Matthew T. Currie,Zhiyuan Cheng,James Fiorenza,G. Braithwaite,T. A. Langdo +5 more
TL;DR: In this paper, the fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations is discussed.
Patent
Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
TL;DR: In this paper, a nonplanar semiconductor device and its method of fabrication is described, which includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate.
References
More filters
Patent
Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
TL;DR: In this article, a method of manufacturing an integrated circuit with a channel region containing germanium was proposed. But the method can provide a double planar gate structure over lateral sidewalls of channel region.
Patent
Strained Fin FETs structure and method
TL;DR: In this paper, a method and structure for a transistor that includes an insulator and a silicon structure on the insulator is presented, where a first gate is positioned on a first side of the central portion of the silicon structure.
Patent
FinFET device incorporating strained silicon in the channel region
TL;DR: In this article, an epitaxial layer of silicon is formed on the silicon germanium FinFET body, and a strain is induced in the silicon crystalline lattice to enhance carrier mobility.
Patent
Strained channel FinFET
TL;DR: In this article, a semiconductor structure includes a fin and a layer formed on the fin, where the first layer includes a first crystalline material having a rectangular cross section and a number of surfaces.
Patent
Mosfets incorporating nickel germanosilicided gate and methods of their formation
TL;DR: The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel mono-silicide.