Journal ArticleDOI
Systematic design for optimization of high-speed self-calibrated pipelined A/D converters
TLDR
In this paper, a multibit, rather than single-bit resolution per-stage architectures have been considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks.Abstract:
High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.read more
Citations
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Journal ArticleDOI
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Boris Murmann,Bernhard E. Boser +1 more
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
Journal ArticleDOI
Integrated chaos generators
TL;DR: This paper surveys the different design issues, from mathematical model to silicon, involved in the design of analog CMOS integrated circuits for the generation of chaotic behavior.
Proceedings ArticleDOI
High-level formal verification of next-generation microprocessors
TL;DR: The application of FPV to validation of the Intel/spl reg/ Pentium/ spl reg/ 4 microarchitecture and some approaches being considered to broaden the application of FV techniques, particularly at a higher level of design abstraction are discussed.
Journal ArticleDOI
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers
Ding-Lan Shen,Tai-Cheng Lee +1 more
TL;DR: A 6-bit 800-MS/s pipelined A/D converter with voltage-mode open-loop amplifiers achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively.
Journal ArticleDOI
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver
TL;DR: A configurable time-interleaved pipeline architecture is presented as an efficient solution for the ADC design in high data rate multi-standard radios and its structure can be configured to accommodate the different sampling rate and dynamic range requirements of both standards.
References
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Book
Analog MOS Integrated Circuits for Signal Processing
Roubik Gregorian,Gabor C. Temes +1 more
TL;DR: In this article, the authors present an overview of the non-ideal effects in Switched-Capacitor Circuits, as well as their application in switch-capacitor circuits.
Journal ArticleDOI
A 10-b 20-Msample/s analog-to-digital converter
TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.
Journal ArticleDOI
Design techniques for high-speed, high-resolution comparators
Behzad Razavi,Bruce A. Wooley +1 more
TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
Journal ArticleDOI
A 15-b 1-Msample/s digitally self-calibrated pipeline ADC
TL;DR: In this paper, a 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented with a radix 1.93, 1 b per stage design, which accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain and capacitor nonlinearity contributing to DNL.
Journal ArticleDOI
A self-calibrating 15 bit CMOS A/D converter
TL;DR: A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described and 15-bit resolution and linearity at a 12-kHz sampling rate is demonstrated.