scispace - formally typeset
Open Access

The 3D Stacking Bipolar RRAM for High Density

Yi-Chung Chen, +3 more
- Vol. 11, Iss: 5, pp 945
TLDR
In this article, two 3D stacking structures built upon bipolar RRAM crossbars are proposed to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance.
Abstract
For its simple structure, high density, and good scalability, the resistive random access memory (RRAM) has emerged as one of the promising candidates for large data storage in computing systems. Moreover, building up RRAM in a 3-D stacking structure further boosts its advantage in array density. Conventionally, multiple bipolar RRAM layers are piled up vertically separated with isolation material to prevent signal interference between the adjacent memory layers. The process of the isolation material increases the fabrication cost and brings in the potential reliability issue. To alleviate the situation, we introduce two novel 3-D stacking structures built upon bipolar RRAM crossbars that eliminate the isolation layers. The bigroup operation scheme dedicated for the proposed designs to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance is also presented. Our simulation results show that the proposed designs can increase the capacity of a memory island to 8K-bits (i.e., eight layers of 32 × 32 crossbar arrays) while maintaining the sense margin in the worst case configuration greater than 20% of the maximal sensing voltage.

read more

Citations
More filters
Journal ArticleDOI

Conduction Mechanism of Valence Change Resistive Switching Memory: A Survey

TL;DR: In this article, the authors conduct a survey on several published valence change resistive switching memories with a particular interest in the I-V characteristic and the corresponding conduction mechanism.
Journal ArticleDOI

RRAM Crossbar Array With Cell Selection Device: A Device and Circuit Interaction Study

TL;DR: In this article, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit, and an optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation.
Journal ArticleDOI

A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks

TL;DR: A Memristor-based dynamic (MD) synapse design with experiment-calibrated memristor models is proposed and a temporal pattern learning application was investigated to evaluate the use of MD synapses in spiking neural networks, under both spike-timing-dependent plasticity and remote supervised method learning rules.
Journal ArticleDOI

Crossbar-Based Memristive Logic-in-Memory Architecture

TL;DR: This paper proposes a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, local information processing is achieved in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross- point selector devices.
Journal ArticleDOI

Analysis of the row grounding technique in a memristor-based crossbar array

TL;DR: Analysis of the row grounding technique shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays.
References
More filters
Proceedings ArticleDOI

A multilayer RRAM nanoarchitecture with resistively switching Ag-doped spin-on glass

TL;DR: In this paper, a multilayer crossbar memory architecture with integrated spin-on glass (methyl-silsesquioxane - MSQ) was used to enhance the potential for very high integration density.
Journal ArticleDOI

Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network.

TL;DR: A compensating circuit is proposed to reduce the impact of wire resistance in a memristor crossbar-based perceptron neural network and shows better recognition rate compared to the previous work when wire resistance is taken into account.
Proceedings ArticleDOI

3D technology based circuit and architecture design

TL;DR: In this article, different stacking techniques are reviewed, followed by an introduction to the possible applications for 3D circuits and systems, including sensor systems, processor-memory systems, network-on-chip designs, and Field-Programmable Gate Arrays.
Proceedings ArticleDOI

Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process

TL;DR: In this paper, a novel approach of via integration with nonetchback (NEB) SOG is investigated to improve performance of unlanded vias, which is a serious problem if zero-overlap metal lines are used.
Journal ArticleDOI

Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background- pattern Dependencies in Pure Memristor Array

TL;DR: A new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme, verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models.
Related Papers (5)