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IEEE transactions on nanotechnology
http://hdl.handle.net/2117/104473
Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G.,
Rubio, A. Crossbar-based memristive logic-in-memory architecture.
"IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3,
p. 491-501.
DOI: 10.1109/TNANO.2017.2691713
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Abstract—The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations has drawn
considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and
its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic
gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly
desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel
processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a
state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily
focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point
selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We present an
analysis of circuit resources, integration density, and logic computation parallelism and prove the proper functioning and potential
capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder (HA) and sum-of-products logic
functions.
Index Terms—computing, crossbar, digital logic, memristor, resistive RAM (ReRAM), resistive switching
I. INTRODUCTION
OR some time now, advances in semiconductor technology have continued to boost both the memory capacity and
computing speed of modern computers. In this regard, among today’s various emerging memory technologies [1], resistive
random access memory (ReRAM) based on resistive switching nanodevices (memristors or memristive devices) [2] stands out as
one of the best-studied and most promising candidates for next-generation nonvolatile memory (NVM) applications [3]-[5].
ReRAM has several attractive properties, such as fast operation, low power consumption, multilevel single-cell storage, and very
high integration density (4F
2
footprint, where F is the minimum feature size of the process technology), owing to the simple,
dense, high-connectivity structure of the nanocrossbar geometry [6], [7]. Additionally, a paradigm shift is needed in computing
systems beyond the classical and so far dominant von Neumann architecture, which separates storage from computation in
distinct units [8]. Data processing in von Neumann systems is normally carried out sequentially, thus requiring a lot of
information exchange and communication between the central processing unit(s) (CPU(s)) and data storage module(s).
Moreover, today’s computers are able to process data at CPU speeds much faster than their memory-access speed, making the
latter a true bottleneck [1]. In an attempt to overcome such limitations and further improve data-processing efficiency, research
has therefore recently begun to focus on brain-inspired (neuromorphic) and, more generally, in-memory computing approaches
[9]-[12].
In this context, the memristor provides an unconventional computing framework, ideally combining resistance-based
information storage and processing in a single device [13]. Several recently published logic circuit design approaches [14]-[20]
use memristors as binary elements in a digital platform, offering functionally complete logic gates and promising to maximize
the benefits of digital computing in future system architectures in which memory and processing co-exist. Nevertheless, mostly
owing to the fact that memristor device technology is still at an early stage, such papers have primarily focused on the digital
logic realization procedure, logic gate implementation, and/or the device-level requirements, and almost all of them have omitted
(or left for future research) the study of the underlying ReRAM organization, the target circuit architecture, and the impact of the
driving circuitry. Further research is necessary at the circuit and/or architecture level to make logic computations as parallel as
possible and thus enable practical application [21], [22]. It would be particularly interesting to see whether and how such logic
design approaches could practically fit in compact memristive storage circuit architectures, exploiting the nonvolatility of
memristors in normal power-off (and thus more energy efficient) logic-in-memory circuits.
In this paper, we aim to address precisely this gap. More specifically, we propose an initial approach to a crossbar-based in-
memory processing system in which the binary information stored in memristors is locally processed in the same unit: i) without
Crossbar-Based Memristive Logic-In-Memory
Architecture
Georgios Papandroulidakis, Ioannis Vourkas, Member, IEEE, Angel Abusleme, Member, IEEE,
Georgios Ch. Sirakoulis, Member, IEEE, and Antonio Rubio, Senior Member, IEEE
F
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the stored data being affected while it is used as logic input; and
ii) keeping the logic result in the same state as the memristors,
where the computation takes place. The basic concept is to take
advantage of a dense crossbar array that is heterogeneous in
terms of its cross-point resistive devices while also using a novel
group-accessing scheme for the selection lines of the target
ReRAM cross-points. Our study particularly focuses on the
ReRAM organization, taking into consideration: i) device-level
memristor properties, by incorporating a threshold-type SPICE-
compatible switching model of bipolar voltage-controlled
memristors [23], [24]; ii) circuit-level properties, by adopting a
functionally complete memristor-based digital logic design
methodology that allows for single-step multi-input parallel
logic computations [20]; and iii) architecture-level details
assuming state-of-the-art high-density and CMOS-compatible
memristor-transistor crossbar geometry with a group-accessed
vertical (which could be thought of as a nano-pillar vertical
gate-all-around or VGAA) transistor as the cross-point selector
underneath each memristive device [25]-[27]. In this way we
achieve: i) memory and logic operations through gate-controlled
resistance switching with no current sneak-paths [28]; ii) a much
smaller cell footprint compared to that of traditionally planar
transistors; and iii) lower operating power compared to that of a
typical passive cross-point array. We justify our choice based on
the memristor logic implementation methodology and comment
on the overall system performance, the integration density, and the achieved parallelism of the logic computations. Finally, we
provide SPICE circuit simulation results to confirm the correct operation of the proposed architecture for examples of sum-of-
product and half-adder (HA) logic functions, highlighting the advantages of the proposed logic-in-memory approach.
II. TOPOLOGY DESCRIPTION AND ANALYSIS
A. Main Topological Features
The general floor plan, showing the basic modules included in the proposed architecture, is given in Fig. 1. Overall, it consists
of two banks of crossbar arrays and their supporting circuit modules. In fact, there are two separate nano-pillar (vertical)
transistor-memristor (1T1R) crossbar arrays, i.e., the memory crossbar, at the bottom of the figure, and the computing crossbar,
which is larger and located at the top. Black dots generally denote cross-points, whereas the horizontal and diagonal rectangles
denote the topology of the transistor selection lines (SLs), i.e., the groups of the select transistors whose gate terminals are
simultaneously driven.
As shown in Fig. 1, the cross-point stacking structure of the memory crossbar array comprises horizontal word lines (WLs) at
the top and vertical bit lines (BLs) at the bottom. Drivers for the WLs and SLs are assumed on opposite sides of the array to
better distribute the layouts of the peripheral circuitry of the CMOS devices used for the selection and application of the voltage
pulses required in each access operation. The inset shows a cross-section of part of a memory word with the ReRAM cells
(shown as a two-material stack without loss of generality) stacked directly on top of group-selected nano-pillar VGAA
transistors. We assume that the ReRAM and the selection device layers are deposited sequentially, with the transistors placed on
the bottom layer (fabricated as front-end transistors) to limit the influences of the parasitic capacitance and resistance and to
minimize the area penalty. An excellent VGAA transistor in this case could be the Si nano-pillar MOSFET by [25], which
demonstrates very good gate controllability and less than 0.1nA leakage current and renders a 4F
2
footprint cross-point cell,
much smaller than the 8-12F
2
of the traditionally planar 1T1R cell. Moreover, group-accessing of the SLs makes it possible to
minimize the number of transistor gate lines from a total of WLs×BLs (when accessing every transistor separately) to only WLs,
thereby simplifying significantly the crossbar fabrication process as specifically discussed in [3].
During the state programming and/or reading memory processes, the input signal simply flows from the WL to the BL. The
latter (depending on the access operation) can be either grounded, left floating, or driven to the sense amplifiers via control
switches, as shown at the bottom of Fig. 1. More specifically, write and read signals are applied to the target WL, whose
respective SL is activated. Reading is a one-step process: all the BLs are driven to the sense amplifiers (one for each BL).
Writing, however, is a two-step process: since the bias direction is mutually reversed in the SET and RESET processes for
bipolar ReRAM cells, they are performed in separate cycles. For instance, the BLs of the ReRAM cells that will be SET are
grounded first, while the rest of the BLs are left floating. In the very next cycle, the previously grounded BLs are left floating and
Fig. 1. Basic topological and organizational features of the proposed
architecture. The insets show a cross-section of the vertical stacking structure
and an indicative signal flow for the computing process.
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the rest are grounded for the RESET process.
On the opposite (top) side of this array, the BLs are
connected to summing amplifiers (whose role will be explained
later), which separate the memory array from the computing
array, found at the top of the system floor plan. The cross-point
stacking structure of the computing array is practically the
same. For the orientation of its top/bottom nanowires we will
assume that the vertical logic input/output lines (LILs and
LOLs, respectively) are at the top of the structure, while the
horizontal routing lines (RLs) are at the bottom. Whether each
logic line is named LIL or LOL depends on whether it is
connected to the summing or sense amplifiers, respectively. As
shown in the respective arrow diagram in the inset, during
computations the input signal follows a circular flow, starting
from the WL of the memory array, moving to the BL and the
LIL through the summing amplifiers, then to the RL, and
finally to the LOL and the sense amplifiers. A set of control
switches makes it possible to drive the output of the summing
amplifiers to the LIL. Depending on the activated SL, the signal
always flows through two 1T1R cells, i.e., through two
memristors (with the same or opposite polarities) and two
transistors, all connected in series via a common horizontal RL.
The basic concept is to employ complementary material
stacking structures in different cross-point cells of the
computing array, i.e., the regular ReRAM stack and the one with a reversed material deposition order [29], [30], in order to have
both forward- and reversely-polarized memristors for the purposes of the computations, which are explained in the following
section.
Furthermore, in order to maintain the high controllability and favorable implementation properties offered by the group-
accessed cross-points, while also permitting the parallel execution of several logic computations, we introduced a novel
geometry for the SL of the computing array, assuming twisted transistor gate nanowires. We will next show that when this
group-selection strategy for the twisted SL is used, there are no disturbing current sneak paths when multiple SLs are driven,
provided the simultaneously driven SLs follow certain acceptable patterns. The simple two-terminal structure of memristors and
the proposed twisted SL topology enable the integration of digital logic computations in the crossbar, where the required serial
ReRAM connection [20] is naturally achieved. However, this novel SL geometry entails a small area overhead. The 1T1R cross-
points with the nano-pillar transistor will require a row- and column-pitch of 3F in order to accommodate the transistor channel
width (1F), the gate surrounding the channel (1F), and the spacer (1F) [30]. Therefore, the computing cross-point cell area
becomes 9F
2
, i.e., 2.25× larger than that of the 4F
2
footprint memory crossbar.
B. Basics of ReRAM-based Logic Circuits
The memristor-based logic computations in our work rely on the memristive logic family proposed by Papandroulidakis et al.
in [20]. It is a parallel-processing, functionally complete logic design scheme, unlike some published sequential processing
approaches, such as the CMOS-like [14], MAGIC [17], and IMPLY [19] logics. It enables the parallel execution of single-step
digital logic operations, exploiting the threshold-dependent switching behavior of memristors and of their simple series
connection. Compared to other parallel processing logic design concepts, such as the MRL proposed by Kvatinsky et al. [18], it
enables the execution of a wider variety of logic operations based on devices with sharp transitions (filamentary or threshold-
type) instead of linear (or homogeneous) switching devices, which generally respond more slowly to the applied input signals
[31].
This memristive logic family uses the total conductance (memductance) of the devices for the parallel computation of AND,
OR, NAND, NOR, XOR, and NOT logic operations. Fig. 2 summarizes the general circuit concept for the implementation of the
aforementioned logic gates and sum-of-products logic functions. Understanding the overall circuit behavior, sometimes based on
collective dynamics of two properly polarized memristors, requires comprehending the switching dynamics of individual
memristors first. To this end, it is worth noting that bipolar memristors with opposite polarities will tend to switch their states in
a reciprocal manner [32]. Hereinafter we will refer to a memristor being forward/reversely polarized (FPM/RPM) when the
voltage is applied to one terminal (top or bottom) with the opposite terminal (bottom or top) being grounded; the bottom terminal
is always denoted by the thick black line in the circuit schematics. Moreover, we will assume that the resistance will decrease
when the memristor is forward-biased and increase when it is reversely biased. In fact, in threshold-type switching memristors
the resistance change-rate is very fast above (and negligibly slow below) the voltage threshold V
SET
or V
RESET
, which determines
Fig. 2. Equivalent memristive circuit implementing: (a) 2-input AND, OR,
NAND, NOR, XOR logic gates and a NOT gate (inverter); (b) a typical sum-
of-products logic function with cascaded logic gates. The dashed rectangle
highlights the use of a single reversely polarized memristor to implement
NOR and NOT logic operations [20].
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the SET (R
OFF
→R
ON
) or RESET (R
ON
→R
OFF
) transition,
respectively.
In this logic design scheme [20] the input voltages consist of:
i) a very low voltage for logic “0”; and ii) a voltage higher than
the threshold V
SET
(and/or |V
RESET
|) for logic “1.” However, the
key idea is that any binary input logic combination is encoded
into a corresponding positive aggregate input voltage (the sum
of the separate input voltages), which is then applied to the
input terminal of the memristive gate, the latter being any of
the six options shown in Fig. 2 (a). We will now briefly
describe how the overall conductance (memductance) can be
used for such logic computations. For example, a single FPM
will switch from a low conductance (L) to a high conductance
(H) if either (or both) of the applied inputs is logic “1,” i.e., if it
exceeds V
SET
. Likewise, when two FPMs are in series, the
composite memductance will rise from a low value (L’) to a
high value (H’) only if both inputs are logic “1,” meaning that
the aggregate input voltage will exceed 2×V
SET
. Apparently,
memductance in these two cases defines the OR and AND
logic operations, respectively, as functions of the aggregate applied input voltage. Thus, requiring the “aggregate” input voltage
explains the use of summing amplifiers in the proposed system. The operation of the rest of the logic gates is explained in a
similar manner in [20]. For instance, a single reversely polarized memristor (RPM) implements the NOR gate since it will switch
from a high conductance (H) to low conductance (L) if either (or both) of the applied inputs is logic “1,” i.e., if it exceeds V
RESET
.
Likewise, when only one logic input is considered, the RPM is equivalent to a NOT gate as well.
Because it is based on memristors connected only in series, this logic design fits well with the structural specifications of the
proposed system. Furthermore, since memristors with opposite polarity are required for some of the logic operations, we assume
that both FPMs and RPMs are readily available inside the heterogeneous (in terms of the cross-point devices) computing array.
This concept of heterogeneity was first proposed in [33]. Logic operations are conducted via conditional switching of nonvolatile
ReRAM cells, featuring no gain. Any logic input combination will have an irreversible effect on the conductance of the
memristors. For instance, if we first apply either “10” or “01” and then, immediately after, “00,” then due to the nonvolatility of
the memristors, the final result will not be correct. Consequently, it is necessary to initialize every gate via a reset pulse in
between each input logic combination, a requirement common to several memristive logic design approaches [17], [19]. To this
end, initialization drivers access the RL and LIL/LOL and are assumed to be distributed around the computing-array. This
notwithstanding, there is no need for a reset step between “01” and “10” inputs. The same is true if the next input, after a “10” or
“01,” is “11,” meaning that algorithmically the efficiency of such logic circuits could be improved by evaluating the number of
“1s” in the input logic combination; however, that falls beyond the scope of this paper.
C. Operational Features and Performance
1) Computing flow characteristics
Having explained the basic topological characteristics of the proposed system, as well as the basics of the logic design scheme
using memristors, we will now provide a specific example to highlight the most important system- and circuit-level operational
properties. The system floor plan shown in Fig. 3 includes a 5×6 1T1R memory array at the bottom and a 5×10 1T1R computing
crossbar at the top. These dimensions are merely indicative for the purposes of this example and do not demonstrate any
particular requirement for the dimensional ratio of the two crossbar banks. However, it is worth noting that, in order to perform
two-input logic computations, two BLs from the memory array should correspond to one LIL from the computing array, i.e.,
there should be 2x as many BLs as LILs. For logic operations with more than two logic input variables, more BLs should
correspond to each LIL and the computing ReRAM cells should be changed accordingly, as described in [20].
In this context, Fig. 3 provides a snapshot of a system supporting only two-input logic operations. Among the selection lines,
those being activated are highlighted in light blue. The aim is to involve the data stored in the memory array (without affecting
them) in multiple single-step parallel logic operations. In this example, we assume that we want to perform two parallel logic
operations with the two red-dot pairs of cells of the activated memory word. The red dots generally denote the cross-point cells
currently being used. Thus, a read voltage pulse (with an amplitude lower than the switching threshold of the memristors) is
applied to the target WL and the corresponding horizontal SL is driven. The BL control switches at the bottom are left floating
and all the BLs are connected to the summing amplifiers at the top. The inset shows the equivalent circuit schematic; the WL
input signal passes through two 1T1R cells before reaching the R
S
input resistors of the summing amplifiers. In this way,
depending on the binary state of these memristors and, thus, on the voltage drop on them, the corresponding BL will have either
a high (logic “1”) or low (logic “0”) voltage. In other words, through the summing amplifiers, we compute a weighted sum of the
Fig. 3. System snapshot highlighting operational details for parallel logic
computations. The inset shows the equivalent circuit schematic between word
lines (WLs) and logic input lines (LILs). A cross-section of two parts of the
computing array indicates the 1T1R cell structure, the memristor polarity, and
the signal flow between LIL and LOL.
![Fig. 2. Equivalent memristive circuit implementing: (a) 2-input AND, OR, NAND, NOR, XOR logic gates and a NOT gate (inverter); (b) a typical sumof-products logic function with cascaded logic gates. The dashed rectangle highlights the use of a single reversely polarized memristor to implement NOR and NOT logic operations [20].](/figures/fig-2-equivalent-memristive-circuit-implementing-a-2-input-2bexbgqu.webp)
