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Proceedings ArticleDOI

Thermal modeling for 3D-ICs with integrated microchannel cooling

TLDR
A fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs, which achieves more than 400× speed up and only 2.0% error in comparison with a commercial numerical simulation tool is presented.
Abstract
Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3D stacked ICs Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs Validation results show the proposed thermal model achieves more than 400x speed up and only 20% error in comparison with a commercial numerical simulation tool We also demonstrate the use of the proposed thermal model for thermal optimization during the IC placement stage We find that due to the thermal-wake effect, tiles are placed in the descending order of power magnitude along the flow direction We also find that modeling thermal-wakes is critical for generating a thermal-aware placement for integrated microchannel-cooled 3D IC It could result in up to 25˚C peak temperature difference according to our experiments Categories and Subject Descriptors B72 [Integrated Circuits]: Design Aids General Terms Design, Performance

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Citations
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Proceedings ArticleDOI

3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling

TL;DR: 3D-ICE, a compact transient thermal model (CTTM) for the thermal simulation of 3D ICs with multiple inter-tier microchannel liquid cooling, is presented, which offers significant speed-up over a typical commercial computational fluid dynamics simulation tool while preserving accuracy.
Journal ArticleDOI

Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits

TL;DR: In this article, the authors provide a vision for codesigning 3D IC architecture and integrated cooling systems and provide a new level of codesign approach with circuit, software and thermal designers working together.
Journal ArticleDOI

3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

TL;DR: 3D-ICE is presented, a compact transient thermal model for liquid-cooled ICs with multi-port cavities, i.e., cavities with more than one inlet and one outlet ports, and non-straight microchannels, and the accuracy has been evaluated against measurements from a real liquid- Cooled 3D-IC, which is the first such validation of a simulator of this genre.
Proceedings Article

Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries

TL;DR: In this paper, the authors proposed a novel compact transient thermal modeling (CTTM) scheme for liquid cooling in 3D ICs via microchannels and enhanced heat transfer cavity geometries such as pin-fin structures.
References
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Journal ArticleDOI

High-performance heat sinking for VLSI

TL;DR: In this paper, a water-cooled integral heat sink for silicon integrated circuits has been designed and tested at a power density of 790 W/cm2, with a maximum substrate temperature rise of 71°C above the input water temperature.
Proceedings ArticleDOI

Temperature-aware microarchitecture

TL;DR: HotSpot is described, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package that shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM.
Journal ArticleDOI

Demystifying 3D ICs: the pros and cons of going vertical

TL;DR: In this paper, the authors present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule.
Journal ArticleDOI

Investigation of heat transfer in rectangular microchannels

TL;DR: In this article, an experimental investigation was conducted to explore the validity of classical correlations based on conventionalsized channels for predicting the thermal behavior in single-phase flow through rectangular microchannels.
Proceedings ArticleDOI

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

TL;DR: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz, designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
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