Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations
Alexandre Levisse,Marc Bocquet,Marco Rios,M. Alayan,Mathieu Moreau,Etienne Nowak,Gabriel Molas,Elisa Vianello,David Atienza,Jean-Michel Portal +9 more
TLDR
This work proposes an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements, and performs extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit.Abstract:
While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Write Termination (WT) circuits are a potential solution to solve these issues. However, previously reported WT circuits do not demonstrate sufficient reliability. In this work, we propose an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements. We perform extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit. Finally, we simulate the effects of the proposed WT circuit with memory traces extracted from real Edge-level data-intensive applications. Overall, we demonstrate 2× to 40× of energy gains at bit level. Moreover, we show from 1.9× to 16.2× energy gains with real applications running depending on the application memory access pattern thanks to the proposed WT circuit.read more
Citations
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Fundamental variability limits of filament-based RRAM
Alessandro Grossi,Etienne Nowak,Cristian Zambelli,C. Pellissier,S. Bernasconi,G Cibrario,Hajjam K. El,R. Crochemore,J. F. Nodin,Piero Olivo,L. Perniola +10 more
TL;DR: In this paper, the variability limits of filament-based resistive RAM arrays in the full resistance range are identified, and extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset and cycling operations are presented allowing the quantification of the intrinsic variability factors.
Proceedings ArticleDOI
Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation
TL;DR: In this article, a self-adaptive write termination circuit is proposed to control the RRAM RESET current, which is defined as the minimal current allowed by the termination circuit in the RESET direction.
Proceedings ArticleDOI
On the Development of MCU-based ad hoc HW Interface Circuitry for Memristor Characterization
TL;DR: Early results from the experience on the design and development of an instrumentation printed circuit board (PCB), designed to provide an ad hoc low-cost solution for measurements on memristor, are presented.
Proceedings ArticleDOI
Embedded measurement of the SET switching time of RRAM memory cells
Fatma Jebali,E. Muhr,M. Alayan,M. C. Faye,Damien Querlioz,Francois Andrieu,Elisa Vianello,G. Molas,Marc Bocquet,J. Portal +9 more
TL;DR: In this paper , an embedded measurement circuit dedicated to the extraction of the SET switching time of RRAM memory cells is presented, which is based on a hybrid 130nm technology with HfO2 BEoL RRAMs, with emphasis on the write termination mechanism and the switching time acquisition thanks to a Time-to-Digital Converter (TDC) shift and capture mechanism.
Journal ArticleDOI
Efficient Identification of Critical Faults in Memristor-Based Inferencing Accelerators
TL;DR: In this article , a misclassification-driven training (MDT) algorithm was proposed to identify critical faults in the crossbar of a DNN model, which can rapidly and accurately identify a large number of FCFs.
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