Showing papers on "Digital electronics published in 1994"

Synthesis and optimization of digital circuits

Abstract: From the Publisher: Synthesis and Optimization of Digital Circuits offers a modern, up-to-date look at computer-aided design (CAD) of very large-scale integration (VLSI) circuits. In particular, this book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and/or area-optimal circuits representations from models in hardware description languages. The book provides a thorough explanation of synthesis and optimization algorithms accompanied by a sound mathematical formulation and a unified notation. The text covers the following topics: modern hardware description languages (e.g., VHDL, Verilog); architectural-level synthesis of data flow and control units, including algorithms for scheduling and resource binding; combinational logic optimization algorithms for two-level and multiple-level circuits; sequential logic optimization methods; and library binding techniques, including those applicable to FPGAs.

Low-power digital systems based on adiabatic-switching principles

Abstract: Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead. >

Symbolic model checking for sequential circuit verification

Abstract: The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is modified to represent state graphs using binary decision diagrams (BDD's) and partitioned transition relations. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5/spl times/10/sup 120/ states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic. >

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates

Abstract: With finer line widths and faster switching speeds, the resistance of on-chip metal interconnect is having a dominant impact on the timing behavior of logic gates. Specifically, the gates are switching faster and the interconnect delays are getting longer due to scaling. This results in a trend in which the RC interconnect delay is beginning to comprise a larger portion of the overall logic stage delay. This shift in relative delay dominance from the gate to the RC interconnect is increased by resistance shielding. That is, as the gate "resistance" gets smaller and the metal resistance gets larger, the gate no longer "sees" the total net capacitance and the gate delay may be significantly less than expected. This trend complicates the timing analysis of digital circuits, which relies upon simple, empirical gate delay equations for efficiency. In this paper, we develop an analytical expression for the "effective load capacitance" of a pc interconnect. In addition, when there is significant shielding, the response waveforms at the gate output may have a large exponential tail. We show that this waveform tail can strongly influence the delay of the RC interconnect. Therefore, we propose an extension of the effective capacitance equation that captures the complete waveform response accurately, with a two-piece gate-output-waveform approximation. >

Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization

Abstract: Motivated by the problem of test pattern generation in digital circuits, this paper presents a novel technique called recursive learning that is able to perform a logic analysis on digital circuits. By recursively calling certain learning functions, it is possible to extract all logic dependencies between signals in a circuit and to perform precise implications for a given set of value assignments. This is of fundamental importance because it represents a new solution to the Boolean satisfiability problem. Thus, what we present is a new and uniform conceptual framework for a wide range of CAD problems including, but not limited to, test pattern generation, design verification, as well as logic optimization problems. Previous test generators for combinational and sequential circuits use a decision tree to systematically explore the search space when trying to generate a test vector. Recursive learning represents an attractive alternative. Using recursive learning with sufficient depth of recursion during the test generation process guarantees that implications are performed precisely; i.e., all necessary assignments for fault detection are identified at every stage of the algorithm so that no backtracks can occur. Consequently, no decision tree is needed to guarantee the completeness of the test generation algorithm. Recursive learning is not restricted to a particular logic alphabet and can be combined with most test generators for combinational and sequential circuits. Experimental results that demonstrate the efficiency of recursive learning are compared with the conventional branch-and-bound technique for test generation in combinational circuits. In particular, redundancy identification by recursive learning is demonstrated to be much more efficient than by previously reported techniques. In an important recent development, recursive learning has been shown to provide significant progress in design verification problems. Also importantly, recursive learning-based techniques have already been shown to be useful for logic optimization. Specifically, techniques based on recursive learning have already yielded better optimized circuits than the well known MIS-II. >

Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment

Abstract: This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties in reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment. >

Current-mode CMOS multiple-valued logic circuits

Abstract: Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >

Noise in digital dynamic CMOS circuits

Abstract: Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits. >

An FPGA for implementing asynchronous circuits

Abstract: Field-programmable gate arrays are a dominant implementation medium for digital circuits, especially for glue logic. Unfortunately, they do not support asynchronous circuits. This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent clocks. We describe Montage, the first FPGA to explicitly support asynchronous circuit implementation, and its mapping software. Montage can be used to realize asynchronous interface circuits or to prototype complete asynchronous systems, thus bringing the benefits of rapid prototyping to asynchronous design. Unfortunately, implementation media for asynchronous circuits and systems have not kept up with those for the synchronous world. Programmable logic devices do not include the special non-digital circuits required by asynchronous design methodologies (e.g., arbiters and synchronizers) nor do they facilitate hazard-free logic implementations. This leads to huge inefficiencies in the implementation of asynchronous designs as circuits require a variety of seperate devices. This has caused most asynchronous designers to focus on custom or semi-custom integrated circuits, thus incurring greater expense in time and money. The net effect has been that optimized and robust asynchronous circuits have not become a part of typical system designs. The asynchronous circuits that must be included are usually designed in an ad-hoc manner with many underlying assumptions. This is a highly error- prone process, and causes implementations to be unnecessarily delicate to delay variations. Field-programmable gate arrays, one of today's dominant media for prototyping and implementing digital circuits, are also inappropriate for constructing more than the simplest asynchronous interfaces. They lack the critical elements at the heart of today's asynchronous designs. Unfortunately, resolving this problem is not just a simple matter of adding these elements to the programmable array. The FPGA must also have predictable routing delay and must not introduce hazards in either the logic or routing. Futhermore, the mapping tools must also be modified to handle asynchronous concerns, especially the proper decomposition of logic to fit into the programmable logic blocks and the proper routing of signals to ensure that required timing relationships are met. Ideally, we need an FPGA that can support both synchronous and asynchronous circuits with comparable efficiency. As a step in this direction we present Montage, an integrated system of FPGA architecture and mapping software designed to support both asynchronous circuits and synchronous interfaces. The architecture provides circuits with hazard-free logic and routing, mutual exclusion elements to handle metastability, and methods for initializing unclocked elements. The mapping software generates placement and signal routing sensitive to the timing demands of asynchronous methods. With these features, the Montage system forms a prototyping and implementation medium for asynchronous designs, providing asynchronous circuits with a powerful tool from the synchronous designer's toolbox.

Efficient implementation of retiming

Abstract: Retiming is a technique for optimizing sequential circuits. It repositions the registers in a circuit leaving the combinational cells untouched. The objective of retiming is to find a circuit with the minimum number of registers for a specified clock period. More than ten years have elapsed since Leiserson and Saxe first presented a theoretical formulation to solve this problem for single-clock edge-triggered sequential circuits. Their proposed algorithms have polynomial complexity; however naive implementations of these algorithms exhibit O(n3) time complexitiy and O(n2) space complexity when applied to digital circuits with n combinational cells. This renders retiming ineffective for circuits with more than 500 combinational cells. This paper addresses the implementation issues required to exploit the sparsity of circuit graphs to allow min-period retiming and constrained min-area retiming to be applied to circuits with as many as 10,000 combinational cells. We believe this is the first paper to address these issues and the first to report retiming results for large circuits.

Method for generating logic modules from a high level block diagram

Abstract: A set of module generators produce optimized implementations of particular circuit logic arithmetic functions for Field Programmable Gate Arrays (FPGAs) or other digital circuits. The module generators allow a circuit designer to spend more time actually designing and less time determining device-specific implementation details. The module generators accept a high level block diagram schematic of the circuit and automatically perform the detailed circuit design, including propagation of data types (precision and type) through the circuit, and low level circuit design optimization using a library of arithmetic and logic functions. The module generators are particularly useful for designs using field programmable gate arrays because of their unique architectures and ability to implement complex functions.

Design techniques for low-voltage high-speed digital bipolar circuits

Abstract: This paper describes design techniques for multigigahertz digital bipolar circuits with supply voltages as low as 1.5 V. Examples include a 2/1 multiplexer operating at 1 Gb/s with 1.2 mW power dissipation, a D-latch achieving a maximum speed of 2.2 GHz while dissipating 1.4 mW, two exclusive-OR gates with a delay less than 200 ps and power dissipation of 1.3 mW, and a buffer/level shifter having a delay of 165 ps while dissipating 1.4 mW. The prototypes have been fabricated in a 1.5-/spl mu/m 12-GHz bipolar technology. Simulations on benchmarks such as frequency dividers and line drivers indicate that, for a 1.5-V supply, the proposed circuits achieve higher speed than their CMOS counterparts designed in a 0.5-/spl mu/m CMOS process with zero threshold voltage. >

Inverter models of CMOS gates for supply current and delay evaluation

Abstract: The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well. >

Complexity of the lookup-table minimization problem for FPGA technology mapping

Abstract: One of the main objectives in the process of mapping a digital circuit onto a LUT-based FPGA structure is minimizing the total number of lookup tables needed to implement the circuit. This will increase the size of the circuit that can be implemented using the available FPGA structure. In this paper, we show that even restricted cases of the lookup-table minimization for FPGA technology mapping are NP-complete (even when K is a small constant), and that it can be solved optimally for all values of K on a tree input in O(min{nK, nlogn}) time where n is the number of nodes in the network and K is the input capacity of the LUT's. Based on our algorithm for trees, we present a polynomial time heuristic algorithm for general Boolean networks. Experimental results confirm substantial decrease on the number of LUT's on a number of MCNC logic synthesis benchmarks compared to the algorithms that allow no or just local exploitation of Boolean properties of the circuit. We obtain 10% to 80% improvement on the number of LUT's compared to the previous algorithms (even though we allow very limited operations, e.g., we do not exploit Boolean properties of the circuits or decompose nodes). >

Representing and modeling digital circuits

Abstract: A computer-aided circuit design tool can be described as a set of algorithms applied to an internal representation of a circuit design or specification in order to answer specific questions or perform certain operations. The representation directly limits the operations that can be performed as well as the accuracy of the resulting answers. This dissertation concerns the development and exploration of one such design representation and shows how it is appropriate for a wide range of circuit design tasks. Along the way, we discover some new techniques for specification, modeling, simulation, and verification of circuits. We especially consider real-time aspects of circuit behavior, and we present some significant enhancements to existing real-time verification algorithms. We present a rich and expressive formalism, called orbital nets, that precisely describes control, timing, and data flow aspects of circuit behavior. We develop the concepts of synchronization, composition, and receptiveness for this formalism, and illustrate how it can be used to specify, model, simulate, and verify digital circuits. We present a textual description language that provides convenient access to orbital nets through parameterization, partial evaluation, and structural and functional decomposition. We present efficient hierarchical real-time simulation and verification algorithms. We prove the equivalence of continuous time and discrete time semantics for orbital nets, and develop some new geometric timing algorithms that exploit concurrency to efficiently verify real-time safety properties.

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

Abstract: The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them. >

Estimation of circuit activity considering signal correlations and simultaneous switching

Abstract: This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results.

A digital read/write channel with EEPR4 detection

Abstract: This device increases the inter-symbol interference (ISI) manageable in a magnetic-media read channel. It re-configures analog and digital circuits by registers to optimize read and write channels. The 51 mm/sup 2/ device is fabricated in a standard 0.8 /spl mu/m single-poly double-metal CMOS process, and contains 128 k transistors. No external components are required for operation other than standard decoupling capacitors. Most of the circuits are active while reading data from the media (data mode), and techniques such as the use of differential analog structures, dedicated supply routes and substrate connections, and shields are employed to control digital interference. >

Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits

Abstract: An electronic circuit test vector generation and fault simulation apparatus is constructed with programmable logic devices (PLD) or field programmable gate array (FPGA) devices and messaging buses carrying data and function calls. A test generation and fault simulation (TGFS) comparator is implemented in the PLD or FPGA consisting of a partitioned sub-circuit configuration, and a multiplicity of copies of the same configuration each with a single and different fault introduced in it. The method for test vector generation involves determining test vectors that flag each of the fault as determined by a comparison of the outputs of the good and single fault configurations. Further the method handles both combinational as well as sequential type circuits which require generating a multiplicity of test vectors for each fault. The successful test vectors are now propagated to the inputs and outputs of the electronic circuit, through driver and receiver sub-circuits, modeled via their corresponding TGFS comparators, by means of an input/output/function messaging buses. A method of fault simulation utilizing the TGFS comparators working under a fault specific approach determines the fault coverage of the test vectors.

Improving the Accuracy of Circuit Activity Measurement

Abstract: A novel measure of activity in digital circuits, called transition density, along with an efficientalgorithm to compute the density at every circuit node, has been proposed in [1]. However, the efficiency of this algorithm is achieved at the cost of accuracy in the density values. This leaves much to be desired for its use in applications which require more accurate activity measurements at each node in the circuit e.g., circuit optimization problems with a low power goal. The complexity of this problem lies in computing the Boolean difference probabilities at each node of the circuit. In this paper, an efficientalgorithm for computing these probabilities is described. This allows the activity measurements, within a circuit partition, to be carried out in a more efficientmanner compared to the well known approach of computing these probabilities. Larger circuit partitions, where each node within a partition is solved accurately with respect to that partition, result in more accurate activity measurements. An efficientcircuit partitioning algorithm, with the goal of maximizing the number of correlated nodes within each partition, has been developed. This allows more accurate measurements compared to a randomly selected set of partitions. These methods have been incorporated in an improved simulator for circuit activity measurement. Some results obtained on the ISCAS85 benchmark circuits are included.

The future of programmable logic and its impact on digital system design

Abstract: Field programmable gate arrays (FPGAs) combine the high-integration benefits of gate arrays with the time-to-market benefits of a user-programmable device. Already a mainstream logic technology, the growth rate of FPGA usage will continue to exceed that of other ASIC technologies. FPGA technology is having a major impact on electronic system design, especially through the use of FPGAs as reconfigurable computing elements. >

On circuits and numbers

Abstract: We establish new, yet intimate relationships between the 2-adic integers /sub 2/Z from arithmetics and digital circuits, both finite and infinite, from electronics. 1) Rational numbers with an odd denominator correspond to output only synchronous circuits. 2) Bit-wise 2-adic mappings correspond to combinational circuits. 3) Online functions /spl forall/n/spl isin/N,x/spl isinsub 2/Z:f(x)=f(xmodd2/sup n/)mod2/sup n/), correspond to synchronous circuits. 3) Continuous functions, /sub 2/Z/spl rarrsub 2/Z, correspond to circuits with output enable. The proof is obtained by constructing synchronous decision diagrams SDDs. They generalize to sequential circuits as classical BDD constructs do for combinational circuits. From simple identities over /sub 2/Z, we derive both classical and new bit-serial circuits for computing: {+,-,/spl times/,1/(1-2x), (1+8x)}. The correctness of each circuit directly follows from the 2-adic definition of the corresponding operator. All but the adders (+,-) above are infinite. Yet the use of reset signals reduces all previously infinite operators to finite circuits. The present work lays out the semantic basis of a new language for describing synchronous circuits. Language 2Z incorporates arithmetic synthesis for some of the above bit-serial operators, and for periodic binary constants (logic from chronograms). It also provides for the powerful deeply binding synchronous enable and reset operators, whose meaning is discussed. >

Synthesis of low power linear DSP circuits using activity metrics

Abstract: Power has become an important optimizing parameter due to increasing use of portable and remote electronic systems. In a CMOS circuit, node activity is directly proportional to the amount of power drawn. We analyze activity metrics at high level for adders and multipliers and derive architectural transformations for synthesizing low power circuits. The goal is to identify data flow graph transformations that reduce overall circuit activity rather than accurate prediction of power consumption. It is shown experimentally that the transformations are power-efficient over many classes of input signals applied to several digital signal processing (DSP) test circuits. >

A low-power chipset for a portable multimedia I/O terminal

Abstract: This paper presents the design of a low-power chipset for a portable multimedia terminal that supports pen input, speech I/O, text/graphics output, and one-way full-motion video. Its power consumption was minimized using an approach that involves optimization at all levels of the design, including extended voltage scaling, reduced swing logic, and switched capacitance reduction through operation reduction, choice of number representation, exploitation of signal correlations, self-timing to eliminate glitching, logic design, circuit design, and physical design. The entire chipset, which performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression, and D/A conversion, is implemented in 1.2 /spl mu/m CMOS and operates from a 1.1 V supply while consuming less than 5 mW. >

A theory of delay-insensitive systems

Abstract: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

Low-pass filter for computing the transition density in digital circuits

Abstract: Estimating the power dissipation and the reliability of integrated circuits is a major concern of the semiconductor industry. Previously, we showed that a good measure of power dissipation and reliability is the extent of circuit switching activity, called the transition density (see ibid., vol. 12, no. 2, p. 310-23, 1993). However, the algorithm for computing the density in the afore-mentioned paper is very basic and does not take into account the effect of inertial delays of logic gates. Thus, as we will show in this paper, the transition density may be severely overestimated in high-frequency applications. To overcome this problem, we model the effect of gate delay on logic signals in the form of a conceptual low-pass filter module that does not allow unacceptably short logic pulses to propagate. Using a stochastic model of logic signals, we then derive the equations required to propagate the transition density through the filter. We will present experimental results that illustrate the validity and importance of these results. >

Mixed-Mode Simulation and Analog Multilevel Simulation

Abstract: Preface. 1: Introduction. 1.1. The Simulation Problem. 1.2. Levels of Simulation for Digital Circuits. 1.3. Levels of Simulation for Analog Circuits. 1.4. Mixed-Mode and Analog Multilevel Simulation. 1.5. Basic Issues in Mixed-Mode Simulation. 1.6. A Survey of Existing Simulators. 1.7. Outline of the Book. 2: Electrical Simulation Techniques. 2.1. Equation Formulation. 2.2. Standard Techniques for Transient Analysis. 2.3. Time-Step Control: Theoretical Issues. 2.4. Time-Step Control: Implementation Issues. 3: Relaxation-Based Simulation Techniques. 3.1. Latency and Multirate Behavior. 3.2. Overview of Relaxation Methods. 4: Iterated Timing Analysis. 4.1. Equation Flow for Nonlinear Relaxation. 4.2. Timing Analysis Algorithms. 4.3. Splice 1.7 -- Fixed Time-Step ITA. 4.4. Circuit Partitioning. 4.5. Global-Variable Time-Step Control. 4.6. Electrical Events and Event Scheduling. 5: Gate-Level Simulation. 5.1. Introduction. 5.2. Evolution of Logic States. 5.3. Characterization of Switching Properties. Subject Index.

CDMA base station modulator for digital cellular mobile communication systems

Abstract: A base station modulator for the digital cellular mobile communication system achieves reduced hardware complexity in a base band QPSK modulating circuit by applying the Multilevel Logic Operation (MLO) which is extended from the conventional binary exclusive-OR operation, to the conventional Base Station Modulator (BSM). The base station modulator includes a plurality of spreaders 621 for QPSK spreading of a voice data stream. These spreaders 621 employ binary-multilevel Logic (MLO) gates instead of multiple binary exclusive-OR gates. The binary-multilevel Logic gate includes a subtractor 510 and a selector 520. The subtractor has one input (-) to which multilevel logic values are applied and one input (+) to which a maximum logic level of the multilevel logic values is applied. The selector has one input to which the multilevel logic values are applied, one input to which the output signal of the subtractor 510 is applied, and one control input to which the binary logic value is applied. If the binary logic value is zero (0), the selector 520 selects and outputs the multilevel logic values, and if the binary logic value is one (1), the selector 520 selects and outputs the output signal from the subtractor 510.

A signature analyzer for analog and mixed-signal circuits

Abstract: While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. In this paper, a novel signature analysis scheme for analog and mixed-signal circuits is proposed. The signatures possess the interesting properly that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold. >

Fast timing simulation of transient faults in digital circuits

Abstract: Transient fault simulation is an important verification activity for circuits used in critical applications since such faults account for over 80% of all system failures. This paper presents a timing level transient fault simulator that bridges the gap between electrical and gate-level transient fault simulators. A generic MOS circuit primitive and analytical solutions of node differential equations are used to perform transistor level simulation with accurate MOS-FET models. The transient fault is modeled by a piecewise quadratic injected current waveform; this retains the electrical nature of the transient fault and provides SPICE-like accuracy. Detailed comparisons with SPICE3 show the accuracy of this technique and speedups of two orders of magnitude are observed for circuits containing up to 2000 transistors. Latched error distributions of the benchmark circuits are also provided.