Showing papers on "Digital electronics published in 2005"

Magnetic Domain-Wall Logic

Abstract: “Spintronics,” in which both the spin and charge of electrons are used for logic and memory operations, promises an alternate route to traditional semiconductor electronics. A complete logic architecture can be constructed, which uses planar magnetic wires that are less than a micrometer in width. Logical NOT, logical AND, signal fan-out, and signal cross-over elements each have a simple geometric design, and they can be integrated together into one circuit. An additional element for data input allows information to be written to domain-wall logic circuits.

Semiconductor Detector Systems

Abstract: 0. Preface 1. Detector systems overview 2. Signal formation and acquisition 3. Electronic noise 4. Signal processing 5. Elements of digital electronics and signal processing 6. Transistors and amplifiers 7. Radiation effects 8. Detector systems 9. Why things don't work A. Semiconductor device technology B. Phasors and complex algebra in electrical circuits C. Equivalent circuits D. Feedback amplifiers E. The diode equation F. Electrical effects of impurities and defects G. Bipolar transistor equations

CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices

Abstract: This paper describes a digital logic architecture for ‘CMOL’ hybrid circuits which combine a semiconductor–transistor (CMOS) stack and two levels of parallel nanowires, with molecular-scale nanodevices formed between the nanowires at every crosspoint. This cell-based, field-programmable gate array (FPGA)-like architecture is based on a uniform, reconfigurable CMOL fabric, with four-transistor CMOS cells and two-terminal nanodevices (‘latching switches’). The switches play two roles: they provide diode-like I –V curves for logic circuit operation, and allow circuit mapping on CMOL fabric and its reconfiguration around defective nanodevices. Monte Carlo simulations of two simple circuits (a 32-bit integer adder and a 64-bit full crossbar switch) have shown that the reconfiguration allows one to increase the circuit yield above 99% at the fraction of bad nanodevices above 20%. Estimates have shown that at the same time the circuits may have extremely high density (approximately 500 times higher than that of the usual CMOS FPGAs with the same design rules), while operating at higher speed at acceptable power consumption. (Some figures in this article are in colour only in the electronic version)

Design considerations for ultra-low energy wireless microsensor nodes

Abstract: This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting source. These requirements place demands on all levels of the design. We propose architecture for achieving the required ultra-low energy operation and discuss the circuit techniques necessary to implement the system. Dedicated hardware implementations improve the efficiency for specific functionality, and modular partitioning permits fine-grained optimization and power-gating. We describe modeling and operating at the minimum energy point in the subthreshold region for digital circuits. We also examine approaches for improving the energy efficiency of analog components like the transmitter and the ADC. A microsensor node using the techniques we describe can function in an energy-harvesting scenario.

Digital Circuit Optimization via Geometric Programming

Abstract: This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits

Abstract: Acknowledgment. Preface. 1. Devices Modeling for Digital Circuits. 1.1. PN JUNCTION. 1.1.1. Reverse Bias Condition. 1.1.2. Foward Bias Condition. 1.2. BIPOLAR-JUNCTION TRANSISTORS. 1.2.1 Basic Operation. 1.2.2. Early Effect or Base Width Modulation. 1.2.3. Charge Effects in the Bipolar Transistor. 1.2.4. Small Signal Model.1.3. MOS TRANSISTORS. 1.3.1. Basic Operation. 1.3.2. Triode or Linear Region. 1.3.3. Saturation or Active Region. 1.3.4. Body Effect. 1.3.5. p-channel Transistors. 1.3.6. Charge Effects in Saturation Region. 1.3.7 Charge Effects in Triode Region. 1.3.8. Charge Effects in Cutoff Region. 1.3.9. Small Signal Model. 1.3.10. Second Order Effects in MOSFET Modeling. 2. Current-Mode Digital Circuits. 2.1. The bipolar Current-mode inverter: basic principles. 2.2. The bipolar Current-mode inverter: Input-Output CharacteristicS and noise margin. 2.2.1. Differential input/output. 2.2.2. Single-ended input/output..2.2.3. Considerations on the non zero input current. 2.2.4. Remarks and comparison of differential/single-ended gates. 2.3. The buffered bipolar Current-mode (ECL) inverter. 2.4. The MOS Current-mode inverter. 2.4.1. Static modeling of the PMOS active load. 2.4.2. Input-output characteristics. 2.4.3. Evaluation of the noise margin. 2.4.4. Validation of the static model. . 2.4.5. The buffered MOS Current-Mode inverter and remarks. 2.5. Fundamental Current-mode logic gates. 2.5.1 Principle of operation of Current-Mode gates: the series gating concept. 2.5.2. Some examples of Current-Mode series gates. 2.5.3. Supply voltage limitations in bipolar Current-Mode gates. 2.5.4. MOS Current-Mode series gates and supply voltage limitations. 2.6. Typical applications of Current-mode circuits. 2.6.1. Radio Frequency applications. 2.6.2. Optic-fiber communications. 2.6.3. High-resolution mixed-signal ICs. 3. Methodologies for complex Current-mode logic gates. 3.1. BASIC CONCEPTS ON THE DESIGN OF A SERIESGATE. 3.1.1. Evaluation of function F(X1...Xn) implemented by a given topology. 3.1.2. Series-gate implementation of an assigned function F(X1...Xn). 3.1.3. Limitations of the general series-gate design approach. 3.2. A GRAPHICAL REDUCTION METHOD. 3.2.1. Basic concepts on the graphical approach in [CJ89]. 3.2.2. A design example. 3.3. an analytical formulation of the design strategy IN [CJ89]. 3.3.1. Analytical interpretation of CPE/NPE. 3.3.2. Analytical simplification through CPE/NPE: an example. 3.3.3. Circuit implementation of the simplified function after CPE-NPE. 3.4. A VEM-BASED REDUCTION METHOD. 3.5. INPUT ORDERING VERSUS DESIGN GOAL. 4. Modeling of Bipolar Current-mode gates. 4.1. Introduction to Modeling methodologies. 4.2. AN EFFICIENT APPROACH FOR CML GATES. 4.3. Simple modeling of THE CML inverter. 4.3.1. Accuracy of the CML simple model. 4.4. Accurate modeling of THE CML inverter. 4.4.1. Accuracy of the CML accurate model. 4.5. Simple AND ACCURATE modeling of THE ECL inverter. 4.5.1. Validation and improvement of the ECL model.4.6. SIMPLE modeling of bipolar CML MUX/XOR gates. 4.6.1. Validation of the MUX/XOR model. 4.6.2.Extension to the MUX/XOR when upper transistors switch. 4.7. ACCURATE modeling of bipolar CML MUX/XOR gates AND EXTENSION TO ECL GATES. 4.8. EVALUATION OF CML/ecl GATES INPUT CAPACITANCE. 4.9. bipolar Current-mode D Latch. 5. Optimized Design of Bipolar Current-mode gates. 5.1. Introduction to optimized methodology in cml gates. 5.2. OPTIMIZED DESIGN OF THE CML INVERTER. 5.2.1. Design with minimum transistor area. 5.2.2. Design with non-minimum transistor area. 5.2.3. Design examples. 5.3. OPTIMIZED DESIGN OF THE ECL INVERTER. 5.4. COMPARISON BETWEEN THE CML AND THE ECL INVERTER. 5.5. OPTIMIZED DESIGN OF BIPOLAR CURRENT-MODE MUX/XOR AND D LATCH. 5.5.1. Design of MUX/XOR CML gates with minimum transistor area. 5.5.2. Design of MUX/XOR CML gates with

Foundations of Analog and Digital Electronic Circuits

Abstract: 1 The Circuit Abstraction 2 Resistive Networks 3 Network Theorems 4 Analysis of Nonlinear Circuits 5 The Digital Abstraction 6 The MOSFET Switch 7 The MOSFET Amplifier 8 The Small Signal Model 9 Energy Storage Elements 10 First-order Transients 11 Energy and Power in Digital Circuits 12 Transients in Second Order Circuits 13 Sinusoidal Steady State 14 Sinusoidal Steady State: Resonance 15 The Operational Amplifier Abstraction 16 Diodes

A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule

Abstract: This paper proposes an architecture of the wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring. The low-power digital IC design inside the wireless endoscopic capsule is discussed in detail. A very large scale integration (VLSI) architecture of three-stage clock management is applied, which can save 46% power inside the capsule compared with the design without such a low-power design. A stoppable ring crystal oscillator with minimal overhead is used in the sleep mode, which results in about 60-muW system power dissipation in sleep mode. A new image compression algorithm based on Bayer image format and its corresponding VLSI architecture are both proposed for low-power, high-data volume. Thus, 8 frames per second with 320*288 pixels can be transmitted with 2 Mb/s. The digital IC design also assures that the capsule has many flexible and useful functions for clinical application. The digital circuits were verified on field-programmable gate arrays and have been implemented in 0.18-mum CMOS process with 6.2 mW

Device optimization for digital subthreshold logic operation

Abstract: Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.

Regenerative and reconfigurable all-optical logic gates for ultra-fast applications

Abstract: All-optical ultra-fast and reconfigurable logic gates have been implemented exploiting simple and low-cost schemes based on nonlinear optical loop mirrors. Regenerative properties of the realised optical logic gates have been demonstrated.

A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits

Abstract: Design of noise detector circuits as compact as standard logic cells is proposed. High-density large-scale digital integrated circuits that embed such built-in noise detectors enable in-depth characterization of dynamic power supply and ground noises. Dependence of power supply and ground voltage drops on the location of active cell rows within 1.8-V standard cell-based digital circuits are consistently measured by 1.8- and 2.5-V built-in detectors fabricated in a 0.18-/spl mu/m CMOS triple-well technology. Measurements also show that ground noise distribution is distinctively more localized than power supply counterparts due to the presence of a substrate.

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

Abstract: The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed Then two new circuits, ie, CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed Both the forward scaling of the active devices and the inverse scaling of interconnection layer, ie, more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples

A low-power high-performance digital circuit for deep submicron technologies

Abstract: This paper presents a novel digital circuit design methodology that can support high-performance and low-power applications. In this method, reusing past internal voltages, signals are charged to Vdd/2 during the pre-charge cycle, so that the voltage of a signal is changed by just Vdd/2 during the evaluation cycle, resulting in a significant reduction in power consumption and propagation delay. The simulation results performed in 0.18/spl mu/m CMOS technology, demonstrate that the new circuit has three times improvement in terms of propagation delay in comparison to the equivalent domino dynamic logics. More importantly, its power consumption is 2.4 times less than that of the domino logics counterpart.

GaN enhancement/depletion-mode FET logic for mixed signal applications

Abstract: The first demonstration of enhancement/depletion (E/D)-mode integrated digital circuits in GaN technology is reported. Specifically, the performance of static divide by 2 circuit implemented in direct coupled FET logic and of a 23-stage ring oscillator, implemented in super-buffered FET logic are presented. The reported E/D technology is potentially suitable for fabrication of mixed signal GaN circuits.

Programmable driver for an I/O pin of an integrated circuit

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals. A comparator is associated with at least one of the pins for comparing the analog voltage level thereon with a reference voltage.

Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

Abstract: This special session adresses the problems that designers face when implementing analogand digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel ofexperts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

A new method for design of robust digital circuits

Abstract: As technology continues to scale beyond 100 nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional circuit optimization methods assuming deterministic gate delays produce a flat "wall" of equally critical paths, resulting in variation-sensitive designs. This paper describes a new method for sizing of digital circuits, with uncertain gate delays, to minimize their performance variation leading to a higher parametric yield. The method is based on adding margins on each gate delay to account for variations and using a new "soft maximum" function to combine path delays at converging nodes. Using analytic models to predict the means and standard deviations of gate delays as polynomial functions of the device sizes, we create a simple, computationally efficient heuristic for uncertainty-aware sizing of digital circuits via geometric programming. Monte-Carlo simulations on custom 32 bit adders and ISCAS'85 benchmarks show that about 10 % to 20 % delay reduction over deterministic sizing methods can be achieved, without any additional cost in area.

Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies

Abstract: In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multioutput Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), tunneling phase logic (TPL), and single electron tunneling (SET), are capable of implementing majority or minority logic very efficiently. However, there exists no comprehensive methodology or design automation tool for general multilevel majority/minority network synthesis. We have built the first such tool, majority logic synthesizer (MALS), on top of an existing Boolean logic synthesis tool. We have performed experiments with 40 MCNC benchmarks. They indicate that up to 68.0% reduction in gate count is possible when utilizing majority logic, with the average reduction being 21.9%, compared to traditional logic synthesis, in which two-input AND/OR gates in the circuit are converted to majority gates.

Method to locate logic errors and defects in digital circuits

Abstract: When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k−1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

Analog+digital phase and frequency detector for phase locking of diode lasers

Abstract: We describe a type of phase and frequency detector employing both an analog phase detector and a digital phase and frequency detector. The analog and digital detectors are mutually exclusive so that only one of them is active at any given time, resulting in a phase detector with both the broad capture range of digital circuits and the high speed and low noise of analog mixers. The detector has been used for phase locking the diode lasers generating the sequence of Raman pulses in an atom interferometer. The rms phase error of the phase lock is about 100 mrad in a 5 Hz–10 MHz bandwidth. The limit set on the interferometer phase resolution by the residual phase noise is 1.1 mrad. Since the digital circuitry is implemented with a programmable logic device the detector can be easily adapted to other experiments requiring frequency/phase stabilization of lasers sources.

DSPs for energy harvesting sensors: applications and architectures

Abstract: Energy harvesting from human or environmental sources shows promise as an alternative to battery power for embedded digital electronics. Digital signal processors that harvest power from ambient mechanical vibration are particularly promising for sensor networks.

Evolutionary design of gate-level polymorphic digital circuits

Abstract: A method for the evolutionary design of polymorphic digital combinational circuits is proposed. These circuits are able to perform different functions (e.g. to switch between the adder and multiplier) only as a consequence of the change of a sensitive variable, which can be a power supply voltage, temperature etc. However, multiplexing of standard solutions is not utilized. The evolved circuits exhibit a unique structure composed of multifunctional polymorphic gates considered as building blocks instead. In many cases the area-efficient solutions were discovered for typical tasks of the digital design. We demonstrated that it is useful to combine polymorphic gates and conventional gates in order to obtain the required functionality.

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

Abstract: This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13-/spl mu/m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.

Single-event mitigation in combinational logic using targeted data path hardening

Abstract: A technique is proposed to selectively harden complex combinational logic circuits to single-event (SE) upsets. Propagation paths with sensitive nodes are identified and hardened while minimizing impact on circuit performance.

Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic

Abstract: The goal of this study is to characterize the impact of soft errors on embedded processors. We focus on control versus speculation logic on one hand, and combinational versus sequential logic on the other. The target system is a gate-level implementation of a DLX-like processor. The synthesized design is simulated, and transients are injected to stress the processor while it is executing selected applications. Analysis of the collected data shows that fault sensitivity of the combinational logic (4.2% for a fault duration of one clock cycle) is not negligible, even though it is smaller than the fault sensitivity of flip-flops (10.4%). Detailed study of the error impact, measured at the application level, reveals that errors in speculation and control blocks collectively contribute to about 34% of crashes, 34% of fail-silent violations and 69% of application incomplete executions. These figures indicate the increasing need for processor-level detection techniques over generic methods, such as ECC and parity, to prevent such errors from propagating beyond the processor boundaries.

Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

Abstract: A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufacturing variations. We introduce the notion of statistical critical paths, which account for both means and variances of performance variation. An optimization engine is used to size gates with the goal of reducing the timing variance along the statistical critical paths. We apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments. We derive a new approximation for the max operation on random variables which is deployed for the faster inner engine. Circuit optimization is carried out using a gain-based algorithm that terminates when constraints are satisfied or no further improvements can be made. We show optimization results that demonstrate an average of 72% reduction in performance variation at the expense of average 20% increase in design area.

Transistor-level optimization of digital designs with flex cells

Abstract: The flex-cell approach, either alone or in combination with standard cells, provides an optimally tuned set of building blocks for integrated circuit design when optimality is measured using accepted and quantifiably definable metrics such as clock speed, die size, and power consumption.

On evolution of relatively large combinational logic circuits

Abstract: Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs.

Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process

Abstract: Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.