Showing papers on "Drain-induced barrier lowering published in 1987"

GaAs FET device and circuit simulation in SPICE

Abstract: We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.

The impact of gate-induced drain leakage current on MOSFET scaling

Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.

A true single-transistor oxide-nitride-oxide EEPROM device

Abstract: A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 A are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.

Subbreakdown drain leakage current in MOSFET

Abstract: Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero V G in thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

Abstract: A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.

Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures

Abstract: The low temperatures current-voltage characteristics of N-channel MOS transistors have been analysed. An excess drain current is observed for intermediate values of drain voltage. This anomalous drain current is explained in terms of substrate freeze-out, since at very low temperatures the MOS structure has a type of floating substrate potential within the depletion region. Due to the increase of the majority carrier current, flowing through the substrate to the source at increasing drain voltage, this substrate potential increases and causes a change of threshold voltage. This change is observed in the current-drain voltage characteristics of the MOSFET. Various experiments, such as measurements of substrate current, effects of temperature, gate and substrate voltages, support this interpretation. MOS transistors with various geometries and various dopings are analysed.

High voltage MOS transistors

Abstract: An insulated-gate, field-effect transistor and a double-sided, junction-gate field-effect transistor are connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity-type material. A top layer of material having a conductivity-type opposite that of the extended drain and similar to that of the substrate is provided by ion-implantation through the same mask window as the extended drain region. This top layer covers only an intermediate portion of the extended drain which has ends contacting a silicon dioxide layer thereabove. The top layer is either connected to the substrate or left floating. Current flow through the extended drain region can be controlled by the substrate and the top layer, which act as gates providing field-effects for pinching off the extended drain region therebetween. A complementary pair of such high-voltage MOS transistors having opposite conductivity-type are provided on the same chip.

Method of manufacturing a field effect transistor device having a multilayer gate electrode

Abstract: This Schottky barrier gate field effect transistor has N + -type source and drain regions formed in the surface area of a GaAs semi-insulation substrate, a channel region formed between the source and drain regions, and a gate electrode formed on this channel region. Particularly, in this Schottky barrier gate field effect transistor, the gate electrode has a first metal portion, which is preferably in Schottky contact with the channel region, and a second metal portion, which stably affixes to the first metal portion. The first and second metal portions are fixed to an insulative portion formed on the channel region.

EPROM device using asymmetrical transistor characteristics

Abstract: An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

Stable substrate bias generator for MOS circuits

Abstract: A circuit for controlling substrate bias voltage of a MOS semiconductor substrate. A first level detector monitors the substrate voltage and when the substrate bias falls below a threshold value, the first level detector couples an oscillator to cause a charge pump to pump charges into the substrate until the threshold level is again reached. A second detector operates as an excess negative voltage detector. This second detector monitors the substrate and when the bias voltage exceeds a predetermined limit, the second detector activates a clamper which drives the substrate toward ground potential until the bias voltage is again under the predetermined limit. By this technique the substrate bias is kept between the first threshold level and the maximum limit level. The first and second detectors are comprised of two transistor circuits, wherein the first leg is comprised of a depletion transistor and at least one enhancement transistor coupled between the supply voltage and the substrate. The second leg is comprised of two depletion transistors coupled between the supply voltage and its return. The junction of the depletion and the enhancement transistor of the first leg is coupled to the gate of one of the depletion transistors in the second leg such that the second leg is biased by the voltage on the junction of the transistors of the first leg which monitors the substrate voltage. The two legs determine the activation point of the detectors. The second detector is made to have at least one more enhancement transistor than the first detector to establish the limit level to be above that of the threshold level.

Output buffer with improved ESD protection

Abstract: An output buffer having improved ESD tolerance is disclosed. The output buffer according to the invention incorporates a field oxide, or other high threshold voltage transistor, having its source-to-drain path connected between ground and the gate of the pull-down transistor, and has its gate connected to the output terminal. The threshold voltage of the high threshold device is greater than the power supply voltage, so as not to turn on during normal operation, but is lower than the BVCBO of the parasitic bipolar transistor associated with the pull-down transistor. The high threshold voltage device turns on with a positive voltage above its threshold appearing at the output terminal, such as occurs in an ESD event, resulting in the gate of the pull-down transistor being biased to ground. This causes the bipolar conduction, and the associated localized J-E heating, to take place away from the surface of the semiconductor, and away from the metal or silicide layers which provide the source of material for melt filaments. A similar high threshold transistor may be provided for biasing the gate of a pull-up transistor to the power supply terminal, having the same effect in the event of an ESD pulse positive relative to the power supply terminal. The high threshold transistors may be constructed as field oxide transistors, and preferably have large channel width-to-length ratios for fast switching.

A model for the electric field in lightly doped drain structures

Abstract: A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor and voltage improvement, indicating the effectiveness of an LDD design in reducing the peak channel field, are used to compare LDD structures with, without, and with partial gate/drain overlap. Approximate equations have been derived that show the dependencies of the field reduction factor on bias conditions and process parameters. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor/voltage improvement and the series resistance are presented for the three cases. Structures with gate-drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate-drain offset can cause the rise of channel field and substrate current at large gate voltages. This offset is also found to be responsible for nonsaturation of drain current. The model has also been compared with two-dimensional simulation results.

The effect of channel implants on MOS transistor characterization

Abstract: MOS device characterization involves the extraction of parameters from electrical measurements. A nonuniform channel doping profile can make such characterization ambiguous since device parameters are usually based upon a uniform doping profile model. In this paper, we solve the one-dimensional Poisson's equation for several doping profiles and show the impact of a nonuniform doping profile on the threshold surface potential, threshold voltage, normal field mobility degradation, and transconductance.

A first-order theory of the static induction transistor

Abstract: A first-order theory of the static induction transistor (SIT) is proposed, which provides a unitary analytical description of its characteristics over the full range of normally encountered biasing conditions. The blocking-state and low-current analysis is based on the original modeling device of considering the intrinsic region of the SIT biased, across its boundary to the drain, by a cosine potential, the maximum value of which is set by a virtual intrinsic-drain electrode. The analytical development leads to design equations for specific SIT parameters such as barrier height, gate efficiency, voltage gain factor and forward blocking gain. The predicted low-current I - V characteristics are consistent with the reported experimental ones. Numerical over-relaxation calculations have been used for a spot-check verification of the analytical model, as well as for extracting the pertinent parameters of the extrinsic region. The intermediate- and high-current analysis of the intrinsic device reveals an interesting electrostatic feedback from the electronic charge in the channel, which carries the drain current, to the potential barrier which controls this current, resulting in triode-like I - V characteristics. The current flows within the limits of a neutral effective channel, which extends from the channel axis to the gates, as the drain current increases. This sets a drain current limitation for the linear range, corresponding to the situation when the channel is completely and uniformly filled with electrons, at the level of its doping concentration. The full-range I - V characteristic of the SIT is basically of the form i + ln i = v , where i and v are normalized drain current and equivalent gate voltage, respectively.

CMOS process flow with small gate geometry LDO N-channel transistors

Abstract: A process for forming lightly doped drains in a CMOS circuit utilizing two photoresist masks is disclosed. After gates for N-channel and P-channel transistors have been formed, an N-implant is effected. A first photoresist mask is used as a source/drain implant is made for the P-channel transistor. Sidewall spacers are formed for the gates of both transistors. A second photoresist mask is used as a source/drain implant is made for the N-channel transistor. The resulting CMOS circuit has an N-channel transistor with a lightly doped drain and a P-channel transistor without a lightly doped drain.

Low voltage dropout regulator

Abstract: A high efficiency dropout regulator (60) drives an output transistor (22) with a PNP transistor (52) if the overhead voltage from input (14) to output (26) is below a predetermined voltage. If the overhead voltage exceeds the predetermined voltage, then a second PNP transistor (64) and an NPN transistor (72) are used to drive the output transistor (22), resulting in a large reduction of power loss. The current drawn from the output transistor (22) by the NPN transistor (72) is returned to the output.

New effects of trench isolated transistor using side-wall gates

Abstract: In order to realize a high performance switching transistor, a new trench isolated transistor with side-wall gates has been developed. In this transistor with a triple-gate structure, the side-wall of the trench is used as an extra-channel region. The new effects of trench isolated transistor with a triple-gate structure have been described. The advantages of this transistor are excellent cutoff characteristics, a small substrate bias effect and high reliability characteristics. It is found that the side-wall gate along the channel edge plays an important role for increasing the gate controllability and for decreasing the concentration of the electric field at the drain.

Hot-carrier drifts in submicrometer p-channel MOSFET's

Abstract: Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.

Semiconductor integrated device having a field-effect transistor type memory cell array and peripheral circuitry structure

Abstract: A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device. In addition, it is possible to lower the resistance of the gate electrode of the second field-effect transistor and to thereby increase the operating speed of the device. Since the first and second field-effect transistors can be formed on a semiconductor substrate having no damage generated thereto, it is possible to increase the dielectric strength of the gate insulator film and to thereby improve the electrical reliability of the device.

Self-aligned gate process

Abstract: Disclosed is a process for producing a field effect transistor to provide a uniformity of spacing between the gate and drain as well as the gate and source.

Hot-carrier induced drain leakage current in n-channel MOSFET

Abstract: Hot-carrier induced drain leakage current in n-channel MOSFET's has been found. Two leakage mechanisms exist at least. The leakage current for one mechanism can be characterized by it, exponential dependence on the drain voltage, approximate proportionality to the stress time, and very small (0.10eV) activation energy. The other mechanism can be characterized by its somewhat ohmic-like dependence on the drain voltage, approximate quadratic dependence on the stress time, and relatively large (0.29eV) activation energy. When stress is imposed by triode-mode operation, the former mechanism is dominant. For pentode-mode operation, the former is followed by the latter. The drain leakage current is observed for conventional, LDD and ALDD (Advanced LDD) structures, although they differ in magnitude. This hot-carrier induced drain leakage current may cause functional failure in DRAM cell or in resistor-load type SRAM cell, while the corresponding degradation in channel conductance may not.

Schottky gate field effect transistor and manufacturing method

Abstract: In a GaAs field effect transistor of the invention, a gate layer is formed on a semi-insulative substrate. The gate layer is made of a conductive material forming a Schottky junction between the substrate and the gate layer. Source and drain regions are formed in the substrate to have a first conductivity type. Barrier layers are formed in the substrate to have a second conductivity type. The barrier layers are formed to surround the source and drain regions, and suppress a current component from leaking from the source and drain regions to the substrate when the field effect transistor is operative.

Driving circuit for cascode BiMOS switch

Abstract: A driving circuit for driving a cascode bype BiMOS switch which includes a bipolar transistor whose collector is connected through a load to a positive electrode of a power source and a field effect transistor whose drain is connected to an emitter of the bipolar transistor and whose source is connected to a negative electrode of the power source. The driving circuit comprises an n.p series body formed by connecting an n-channel field effect transistor in series relation with a p-channel field effect transistor, wherein a mid-point to the n.p series body is connected to a base of the bipolar transistor. A drain and a source of the n-channel field effect transistor are connected to a D.C. power source and the mid-point, respectively. A drain and a source of the p-channel field effect transistor are connected to the mid-point and the negative electrode of the power source, and a gate of the field effect transistor and gates of the n-channel and p-channel field effect transistors are connected to an input terminal, whereby the cascode type BiMOS switch is driven by a single positive or negative signal.

On charge nonconservation in FET's

Abstract: It is shown that source and drain charges are not state variables in an FET, especially for source-drain voltages near zero. This behavior, observed in the model proposed in [2], is a genuine manifestation of the physics of FET's and is not a sign of improper behavior in a circuit simulator. However, if necessary, one may construct a model having these charges as state variables by introducing a current generator that transfers charge from source to drain internally without producing extra currents in the leads of the device.

Method for fabricating edge channel FET

Abstract: Edge channel FET structural geometry and processing is disclosed. A plurality of mesa stacked horizontal layers are provided including source and drain semiconductor layers (74, 76) separated by an insulator layer (75) and having exposed edges (78, 80) at a generally vertical side (83) of the mesa. A generally vertical semiconductor layer (84) extends along the side of the mesa over the exposed source and drain layer edges and forms a channel (93). A gate layer (91, 92) on the channel controls depletion region spreading in the channel layer to control conduction therethrough between the source and drain layers. Channel length is extremely small, as low as 0.1 micron. Ohmic contacts (87, 90) to the source and drain layers are defined several microns away from the conducting channel, resulting in considerable reduction in fabrication complexity, as well as improved reliability. Fabrication and alignment of the gate to the active channel layer is simplified.

Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment

Abstract: A method of forming semiconductor devices wherein a gap is formed beneath the field oxide between the channel stop implant and source/drain regions in the moat or active element region to prevent or minimize encroachment of channel stop impurity toward the source/drain regions to form spurious pn junctions and/or reduce the active element region.

Resonant tunnelling gate field-effect transistor

Abstract: A new negative differential resistance field-effect transistor concept, based on resonant tunnelling, is demonstrated. The gate of this novel device consists of an AlAs/GaAs double barrier. The drain current against drain and gate voltages exhibit a peak due to the quenching of the resonant tunneling gate current. Thus, in addition to negative conductance, this structure exhibits negative transconductance, a uniquie feature in an n-channel device.

Metal-oxide-semiconductor (mos) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit

Abstract: A metal-oxide-semiconductor (MOS) field effect transistor comprises monocrystalline, doped silicon zones which are formed between gate electrodes and the field oxide zones by selective epitaxy and which simultaneously serve as diffusion sources for the formation of source and drain zones in the substrate and as terminal zones for silicide source and drain terminals. This terminal technology serves to form particularly planar structures, with a high integration density, which structures are characterized by reduced drain field strength, low series resistances and a small danger of substrate short circuits. Processes for the formation of this structure in CMOS circuits are simple to perform. The present invention can be applied to all NMOS, PMOS and CMOS circuits.

Integrated circuit electrostatic discharge input protection

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents generated by electrostatic discharge through handling or otherwise, is provided by a circuit structure at each input pad of an integrated circuit chip. One such feature includes the use of a barrier layer of polysilicon material to make an electrical contact between source and drain diffusions of a protective transistor and their respective aluminum conductors, in order to increase the amount of current that can be handled at such contacts without the aluminum conductor fusing though a diffusion into the substrate. Another such feature is to provide an initial, and perhaps only, protective transistor that has a very narrow channel between source and drain diffusions to allow a reversible breakdown to reduce the voltage across it to within, or nearly within, the maximum voltage that the protected thin gate oxide transistor can handle without being damaged. Further, current concentrations in the protective transistor are minimized by the use of elongated diffusions and associated solid elongated conductors having rounded corners.

The resonant-tunneling field-effect transistor: A new negative transconductance device

Abstract: A new field-effect transistor with a resonant-tunneling barrier in the gate is presented. The gate and the drain currents versus gate voltage exhibit peaks when the resonant-tunneling gate current is quenched. Thus, in addition to negative differential resistance, this structure also exhibits negative transconductance, a unique feature in an n-channel device. Also, by proper gate bias, the same resonance of the double barrier can be used to produce two peaks in the drain current versus drain voltage characteristic at nearly the same current level. This is a very desirable feature for many applications.