Showing papers on "Gate driver published in 1999"

Semiconductor memory device allowing high-speed operation of internal data buses

Abstract: A current mirror-type load circuit is provided for a global data line pair. A read gate amplifier used as a block select gate for each of the local data line pairs. A read gate amplifier includes a MOS transistor having its gate connected to a corresponding local data line. A data write driver writes the logic-inverted data of the write data upon equalization after the data write operation. A high-speed access becomes possible by reducing the time required for reading of data and by reducing the write recovery time.

Coreless printed circuit board (PCB) transformers for power MOSFET/IGBT gate drive circuits

Abstract: Gate drive circuits for modern power electronic switches, such as MOSFET and insulated gate bipolar transistor (IGBT), often require electrical isolation. This paper describes the modeling and experimental results of some coreless printed circuit board (PCB)-based transformers that can be used for MOSFET and IGBT devices at high-frequency (500 kHz to 2 MHz) operation. PCB-based transformers do not require the manual winding procedure and thus simplify the manufacturing process of transformer-isolated gate drive circuits. With no core loss, coreless transformers are found to have favorable characteristics at high-frequency operations. This project demonstrates an important point that the size of the magnetic core can approach zero and become zero when the frequency is sufficiently high.

Distributed MOSFET structure with enclosed gate for improved transistor size/layout area ratio and uniform ESD triggering

Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

Series connection of IGBT's with active voltage balancing

Abstract: This paper describes an active gate drive circuit for series-connected insulated gate bipolar transistors (IGBTs) with voltage balancing in high-voltage applications. The gate drive circuit not only amplifies the gate signal, but also actively limits the overvoltage during switching transients, while minimizing the switching transients and losses. In order to achieve the control objective, an analog closed-loop control scheme is adopted. The closed-loop control injects current to an IGBT gate as required to limit the IGBT collector-emitter voltage to a predefined level. The performance of the gate drive circuit is examined experimentally by the series connection of three IGBTs with conventional snubber circuits. The experimental results show the voltage balancing by an active control with wide variations in loads and imbalance conditions.

Comparison of high-power IGBT's and hard-driven GTO's for high-power inverters

Abstract: This paper compares hard-driven gate-turn-off thyristors (IGCTs) and high-power insulated gate bipolar transistor (IGBT) modules in a two-level pulsewidth modulation inverter. The structure, fundamental operation and specific characteristics of the considered devices are shown. Simulations enable a loss comparison of IGCTs and IGBTs in a 1.14 MVA inverter at switching frequencies of f/sub s/=250 Hz/500 Hz. The evaluation of device characteristics is the basis for a derivation of potential applications.

Oscillation effects in IGBT's related to negative capacitance phenomena

Abstract: Insulated gate bipolar transistors (IGBT's) are inherently unstable at high collector voltages due to negative gate capacitance values. We investigate IGBT gate voltage oscillations by experiment and through computer simulation. In addition, we show that under certain gate circuit conditions, gate voltage oscillations can lead to already observed collector current imbalance effects.

Fast-clamped short-circuit protection of IGBT's

Abstract: Identification of fault current during the operation of a power semiconductor switch and activation of suitable remedial actions are important for reliable operation of power converters. A short circuit is a basic and severe fault situation in a circuit structure, such as voltage-source converters. This paper presents a new active protection circuit for fast and precise clamping and safe shutdown of fault currents of the insulated gate bipolar transistors (IGBTs). This circuit allows operation of the IGBTs with a higher on-state gate voltage, which can thereby reduce the conduction loss in the device without compromising the short-circuit protection characteristics. The operation of the circuit is studied under various conditions, considering variation of temperature, rising rate of fault current, gate voltage value and protection circuit parameters. An evaluation of the operation of the circuit is made using IGBTs from different manufacturers to confirm the effectiveness of the protection circuit.

Gate circuit and gate circuit control method

Abstract: PROBLEM TO BE SOLVED: To provide a gate driving circuit for shortening a switching period without destroying a gate type semiconductor element. SOLUTION: This gate circuit 1 is provided with the gate type semiconductor element 5, a first on gate circuit for supplying a first on-gate current to the gate type semiconductor element 5 and a second on-gate circuit for starting the supply of a second on-gate current to the gate type semiconductor element 5 after the lapse of prescribed time after starting the supply of the first on-gate current.

Power supply control device for protecting a load and method of controlling the same

Abstract: When the power supply from a power source 101 to a load 102 is controlled in a switching manner by a semiconductor switch QA, reference voltage generating means (QB, Rr) generates a reference voltage (VDSB) having a voltage characteristic substantially equivalent to that of a voltage between the terminals of the semiconductor switch QA being connected to a predetermined load. Detecting means CMP1 detects a difference between the voltage (VDSA) between the terminals of the semiconductor switch QA and the reference voltage (VDSB). Control means which consists of the gate driver 111 amd CMP1 performs an on/off control of the semiconductor switch QA in accordance with the difference between the voltage (VDSA) between the terminals of the semiconductor switch and the reference voltage (VDSB).

Driving device and driving method for a display device

Abstract: Disclosed is a display device (e.g., a liquid crystal display), and an apparatus and a method for driving the display device. The LCD includes an LCD panel having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of TFTs each having a gate electrode connected to one of the gate lines and a source electrode each connected to one of the data lines; a gate driver for sequentially supplying gate drive signals to the gate lines to turn the TFTs ON; and a data driver for dividing the data lines into a certain number of blocks, each block having a predetermined number of data lines, and applying image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block. The apparatus includes the gate driver and the data driver. The method includes the steps of sequentially supplying the gate drive signals to the gate lines to turn the TFTs ON; and applying the image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block.

Surge preventing circuit for an insulated gate type transistor

Abstract: A first Zener diode group, connected between drain and gate terminals of a power MOSFET, causes breakdown in response to a surge voltage applied to the drain terminal. A resistor, provided between the gate terminal of the power MOSFET and a gate control unit, prevents current from flowing from the drain terminal of the power MOSFET to the gate control unit in an event of the breakdown of the first Zener diode group. A second Zener diode group, connected between source and gate terminals of the power MOSFET, has a breakdown voltage lower than the gate withstand voltage of the power MOSFET. The second Zener diode group clamps the gate voltage against the breakdown of the first Zener diode group.

Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

A silicon carbide CMOS intelligent gate driver circuit with stable operation over a wide temperature range

Abstract: In this paper, we present the design and fabrication of a high-temperature silicon carbide CMOS intelligent gate driver circuit intended for high-power switching applications. Using a temperature-insensitive comparator, several functions including overvoltage and undervoltage, as well as short- and open-load detection, are provided, all of which are operational up to 300/spl deg/C. These integrated circuits are ideally suited for harsh and high-temperature environments such as automotive and aircraft jet engines.

Liquid crystal display having different common voltages

Abstract: Disclosed is a liquid crystal display that prevents a flicker by employing a circuit with adjustable resistors in the output of a common voltage generator. The common voltage generator supplies two distinct common voltages, one common voltage being supplied to a common electrode at a point that is physically close to the output of a gate driver, and a second common voltage being supplied to a point that is physically further from the output of the gate driver than the point where the first voltage is applied. These points where the first common voltage and the second common voltages are applied are electrically coupled via an internal panel resistor. A flicker is prevented by adjusting the variable resistors so that the difference between the first and second common voltages is equal to the difference in the kickback voltages at the first point and at the second point.

Gate drive circuit for isolated gate devices and method of operation thereof

Abstract: A gate drive circuit for an isolated gate device, a method of driving the same and a switch-mode power supply employing the circuit or the method. In one embodiment, the circuit includes: (1) a capacitor, having a first terminal coupled to a source of drive voltage and a second terminal coupled to a gate of the isolated gate device, that stores a charge therein when the drive voltage maintains the isolated gate device in an "on" state and (2) a conductive path, leading from the first terminal to an output terminal of the isolated gate device and enabled when the isolated gate device is to be transitioned from the "on" state to an "off" state, that provides a negative off-bias voltage to the gate thereby to avoid spurious turn-on of the isolated gate device.

Solid-state image sensing apparatus and method of operating the same

Abstract: In a solid-state image sensing apparatus, each pixel includes a photodiode, a MOS amplifier whose gate receives photo-charge generated by the photodiode, and a MOS switch for controlling connection between the photodiode and the gate of the MOS amplifier, and transference of the photo-charge from the photodiode to the gate of the MOS amplifier is performed under a condition that a channel is formed under the gate of the MOS amplifier.

High performance active gate drive for IGBTs

Abstract: An active drive circuit for high power IGBTs provides optimized switching performance for both turn-on and turn-off by incorporating a three-stage action to improve performance characteristics. The gate drive circuit includes a semiconductor switch such as a MOSFET connected in series with a low resistance gate turn-on resistor between the supply line and the gate input line, and a parallel connected bipolar transistor. During the first and third stages of turn-on, the MOSFET switch is turned on to provide rapid charging of the gate, whereas during the second stage the bipolar transistor is turned on to provide a controlled level of current charging of the gate. Similarly, a switch such as an MOSFET is connected in series with a low resistance gate turn-off resistor between the turn-off supply voltage line and the gate input line, and a bipolar transistor is connected in parallel therewith across the supply line and the gate input line. During the first and second stages of turn-off, the MOSFET switch is turned on to provide rapid discharging of the gate whereas during the second stage the bipolar transistor is turned on to provide a controlled level of discharge current from the gate.

Method and structure for in-line monitoring of negative bias temperature instability in field effect transistors

Abstract: A MOSFET test structure and associated electronics for rapidly heating the MOSFET gate oxide and for applying a stress voltage to the gate. The structure has at least one polysilicon gate with two spaced contacts that permit a heating current to flow through the gate thus rapidly raising the gate temperature to a desired level. External electronics permit applying a measured stress voltage to the gate. The structure is particularly useful in NBTI testing of p-MOSFETs.

Transformerless capacitive coupling of gate signals for series operation of power MOS devices

Abstract: A reliable configuration for triggering a series string of power MOS devices without the use of transformer coupling is presented. A capacitor is inserted between the gate and ground of each MOSFET, except for the bottom MOSFET in the stack. Using a single input voltage signal to trigger the bottom MOSFET, a voltage division across the network of device capacitance and inserted capacitances triggers the entire series stack reliably. Design formulae are presented and simple circuit protection is discussed. Simulation shows reliable operation and experimental verification is presented. Application of the method is applied to series IGBTs.

Gate drive circuit for voltage driven switching element

Abstract: (57) [Summary] Di / dt, d at the time of IGBT switching while suppressing increases in IGBT switching time and loss. v / dt is suppressed. A driving unit for amplifying a signal for controlling a switching operation of a voltage-driven switching device including an IGBT, a unit for detecting a gate voltage of the IGBT, and an output voltage when the driving unit is turned on (off). Voltage drop (rise) that gradually falls (rises) over time Means for increasing the output voltage and a voltage increasing (falling) means for gradually increasing the output voltage, and switching from the voltage decreasing (rising) means to the voltage increasing (dropping) means in accordance with a detected value of the gate voltage of the IGBT. By doing, di / dt and dv / dt when the IGBT is on (off) are suppressed.

Active gate control strategy of series connected IGBTs for high power PWM inverter

Abstract: This paper describes an operation of series connected IGBT gate drive circuit with a closed loop voltage control in high voltage inverter applications. The purpose of voltage control is to instantaneously limit large overvoltage applied to certain IGBTs in inverter valves during switching transients and off-state IGBT voltages and to maintain the voltage to an acceptable level. The performance of the gate drive circuit is examined experimentally by the series connection of four different rated IGBTs with conventional snubber circuits. The experimental results show the voltage balancing by the voltage control with wide variations in imbalance conditions.

High efficiency high frequency resonant gate driver for power converter

Abstract: A driver circuit for a high frequency switching circuit such as a converter for a gas discharge lamp includes a resonant circuit which transfers energy from the parasitic input capacitance of one or more power switching devices (Sa, Sb) during switching of the latter. The energy transfer prevents dissipation of the capacitive energy in the driver circuit which may otherwise destroy one or more components of the driver circuit. The resonant circuit includes a discrete inductor (Lx) in the driver circuit. Preferably, one or more discrete capacitors (Cxa, Cxb) are also included within the driver circuit to maintain resonance at a given frequency regardless parasitic capacitance variation.

1.2 kV trench insulated gate bipolar transistors (IGBT's) with ultralow on-resistance

Abstract: In this letter, we report the full development of 1.2 kV Trench IGBT's with ultralow on-resistance, latch-up free operation and highly superior overall performance when compared to state of the art IGBT's. The minimum forward voltage drop at the standard current density of 100 A/cm/sup 2/ was 1.1 V for nonirradiated devices and 2.1 V for irradiated devices. The maximum controllable current density was in excess of 1000 A/cm/sup 2/.

CMOS output buffer with negative feedback dynamic-drive control and dual P,N active-termination transmission gates

Abstract: An output buffer for a line driver uses transmission gates for active termination. A large p-channel driver is pulsed on during a low-to-high output transition, but this driver is turned off once the output voltage reaches a threshold. A feedback circuit includes a sensing inverter that has its input connected to the output node. The sensing inverter causes the gate of the p-channel driver to be driven high once the output swings past the threshold. A similar n-channel driver transistor is pulsed on during a low-going output transition but is disabled by a feedback circuit that senses the output voltage falling below a threshold. A pullup transmission gate is also connected between the output and the power supply, while a pulldown transmission gate is connected between the output and ground. Each transmission gate contains a p-channel and a n-channel transistor in parallel. The sizes of the p-channel and n-channel transistors in the transmission gate is sufficiently small to provide a resistance of 25 to 30 ohms. Both transistors in the pullup transmission gate are turned on when the output is driven high, while both transistors of the pulldown transmission gate are turned on when the output is driven low. Having both n and p transistors of the transmission gate on provides a more linear resistance across the voltage swing of the output. Since termination of about 25-30 ohms is provided by the transmission gate, an external series resistor is not needed for dampening. When driving large capacitive loads, several nanoseconds of R-C delay can be saved.

Power supply apparatus of an LCD and voltage sequence control method

Abstract: A power supply for an LCD and a voltage sequence control method in which the sequence for voltages applied to a gate driver IC for outputting a driving voltage of an LCD panel is controlled by arranging a switching element between a DC-to-DC converter and the gate driver IC so as to switch a turn-on voltage to a turn-off voltage to be applied to the gate driver IC, and a latch up is prevented by arranging diodes in reverse and forward directions to the lines for applying the turn-on and turn-off voltages respectively so that the applied voltage is not deviated from the latch up preventing scope. Voltages are applied or removed from the gate driver IC in accordance with a predetermined sequence, and an abnormal voltage is prevented from being applied in an early stage of driving, to thereby stabilize the LCD panel operation.

Drive circuit for an active matrix liquid crystal display device

Abstract: A gate driver circuit for driving an active matrix LCD device is adapted to a mutli-scan function. The gate driver circuit includes a memory circuit including a plurality of (N) memory cells each disposed for a corresponding one of gate lines in the LCD device, a scan circuit including N transfer elements, and a gate line drive circuit including N logic units effecting a specific logic operation. The logic units consecutively drives gate lines in the central area in the picture writing period for displaying a picture image, and drives gate lines in the top and bottom peripheral areas at once for displaying black color. The LCD device displays the picture image on the central area on a selected number of pixel elements for adapting an image source.

Display device and imaging device

Abstract: PROBLEM TO BE SOLVED: To provide a display device and an imaging device capable of increasing an area ratio of the display element or the imaging element to a driver in relation between the display element or the imaging element and the driver for driving them, and of arranging a display element or an imaging element in an approximately center. SOLUTION: A gate driver 2 for scanning gate lines GL1-GL2n of a liquid crystal display element 1 sequentially comprises an odd driver 2o and an even driver 2e. In the odd driver 2o, a first stage inputs a start signal IN and outputs a high level selection signal in accordance with a control signal Φ1, CK to the gate line GL1 on the first line. A j-th stage (j=2-n) inputs a signal supplied from the even driver 2e through the gate lines GL (2j-2) and outputs a high level selection signal to the gate lines GL (2j-1) in accordance with the control signal Φ1, CK. In the even driver 2e, each of the stages 2i (i=1-n) inputs a signal supplied from the odd driver 2o through the gate lines (2i-1) and outputs a high level selection signal to the gate lines GL2i in accordance with the control signal Φ2, CK.

Transmission gate circuit

Abstract: When a power supply terminal ( 10 ) is grounded, a circuit ( 101 ) is in the OFF state, and a high potential is transferred from a circuit ( 3 ) to a bus line (BL), the high potential is transferred to a node ( 100 ) via the source of a transistor (P 1 ), back gate (Nw), and transistor (P 2 ). A NAND circuit (NA 1 ) always outputs a control signal (VGP) of a level equal to the node ( 100 ) to the gate of the transistor (P 1 ) to turn non-conductive the transistor (P 1 ). Hence, a current path from a terminal (B) to a terminal (A) or from the terminal (B) to the back gate (Nw) is cut off to prevent wasteful current consumption.

Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates

Abstract: A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

Controller for liquid crystal display panel, control method, and liquid crystal display device

Abstract: PROBLEM TO BE SOLVED: To enable to display surely picture data from the leading of a liquid crystal display panel by detecting a data-enable signal being made active while picture data is supplied to a panel, and controlling display timing. SOLUTION: A D flip-flop 20 is synchronized with a clock signal from a picture data supplying source, latches a data-enable signal ENAB, and detects it. When an output of the D flip-flop 20 is made to be a H level, that is, a data-enable signal ENAB is supplied from the picture data supplying source, a timing making circuit 32 outputs a clock D-CLK for data driver, a start pulse D-SP for data driver, a latch pulse LP, picture data DATD, a clock G-CLK for gate driver, and a start pulse G-SP for gate driver so that display timing of picture data in a liquid crystal display panel can be controlled with display timing based on the data-enable signal ENAB outputted from an AND circuit 21.