Showing papers on "Gate oxide published in 1976"

The use of charge pumping currents to measure surface state densities in MOS transistors

Abstract: A method is described for determining the surface-state density at the oxide interface in the channel of an MOS transistor from the charge pumping current flowing to the substrate when gate pulses are applied. From this simple measurement the surface state density can be determined as a function of gate voltage and if a quasi-static C-V characteristic is also measured for the gate of the transistor then the voltage distribution can be converted into an energy distribution. Representative results obtained on a set of commercial transistors show a large increase in the surface-state density near the middle of the band-gap after negative-bias thermal-stressing.

Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

Abstract: Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.

Threshold voltage of narrow channel field effect transistors

Abstract: A new effect associated with Metal-Oxide-Silicon Field-Effect-Transistors (MOS-FET's) is presented in this paper. MOS-FET's show an increase of threshold voltage with decreasing ratio of channel width to gate depletion width. This narrow channel effect is explained by means of geometrical edge effects. With decreasing channel width the transition from the field oxide depletion region to the gate oxide depletion region becomes comparable to the gate width and cannot be neglected in the derivation of the threshold voltage equation. A theoretical model is given to explain the influence of decreasing channel width on the threshold voltage as well as on other electrical parameters. This theoretical model is in good agreement with experimental results given in this paper.

Memory field effect storage device

Abstract: A n-channel storge field effect election device having a floating gate completely surrounded by insulating material is described. During writing in the storage the floating gate is charged negatively by hot elections generated in its own channel by channel injection. After charging, and particularly during reading, the gate inhibits drain to source current, by means of its negative charge.

Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device

Abstract: A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.

VMOS Floating gate memory device

Abstract: A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and address lines by thin oxide layers. Data is written into the cell when hot electrons are injected into the gate oxide near the drain junction and attracted to the floating gate which has been charged positive by capacitance coupling from the word line. The hot electrons are generated from the channel current via impact ionization at the pinched-off drain junction.

Random access memory cell with different capacitor and transistor oxide thickness

Abstract: An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal silicon oxide which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

Complementary insulated gate field effect transistor structure and process for fabricating the structure

Abstract: A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Qss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.

Electrically alterable floating gate semiconductor memory device with series enhancement transistor

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by two address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming.

Minimum size ROM structure compatible with silicon-gate E/D MOS LSI

Abstract: Describes a new read-only memory (ROM) with minimum geometry. A cascade ratioless circuit configuration is used, which is process compatible with silicon-gate metal-oxide semiconductor (MOS) large-scale integration (LSI) using depletion load MOSTs. The content of a memory cell in the new ROM is determined by the choice of the MOST threshold mode, either an enhancement or depletion mode; this differs from the conventional ROM structure where the content of a memory cell is distinguished by the thickness of gate oxide. The size of a single bit of the ROM is only 196 /spl mu/m/SUP 2/ and is a reduction of 45 percent compared to a conventional silicon-gate ROM.

Double implanted planar mos device with v-groove and process of manufacture thereof

Abstract: An MOS transistor has a short vertical channel extending along the thickness of the transistor wafer and along the wall of a V-shaped groove, and has laterally disposed source, drain and gate electrodes on the same surface of the wafer. The channel is formed by a double ion implantation, or double diffusion operation. The source and drain electrodes are disposed on the same surface of the wafer and on opposite sides of the V-groove. The transistor has the speed capability of a bipolar transistor and high device density of a silicon gate MOS device, and has a shorter channel length (less than 1 micron) and higher punch-through voltage than has been previously available in a planar-MOS device.

Insulated gate type field effect transistors

Abstract: In an insulated gate type field effect transistor comprising spaced source and drain regions, an insulating film between the source and drain regions and a gate electrode mounted on the insulating film, an inverted frustum shaped polycrystalline semiconductor layer is formed on the insulating film and the gate electrode is mounted on the polycrystalline semiconductor layer.

Defect spatial distributions in annealed ion‐implanted silicon measured by a transient capacitance technique

Abstract: Defect spatial distributions of extremely low concentration were measured, for the first time, by a transient capacitance technique in ion‐implanted MOSFET’s Aluminum gate FET’s were ion implanted through the gate oxide with 1×1012 of 28Si+ ions/cm2 at 310 keV The devices were annealed at 650 °C before Al was put down Energy levels for the residual defects after annealing were obtained at Ec−029, Ec−045, Ec−054, and Ev+052 eV, respectively Then the in‐depth distribution for each level was measured to a concentration of 1012/cm3 by varying the gate voltage The profile of defect distribution shows that the annealing after low‐dose implantation differs from the regrowth of the amorphous layer caused by heavy implantation and that most of the residual defects remain in the bulk rather than at the interface

MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions

Abstract: An MOS field effect transistor includes a substrate in which source and drain regions are formed. A thick silicon dioxide layer is selectively formed on the upper surface of the substrate, so that in the resulting structure, the junction depth associated with the source and drain regions is selectively greater at contact locations and at the portions of the source and drain regions that are in contact with the active channel.

Electrically alterable floating gate semiconductor memory device

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by row address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon.

Self-aligned double implanted short channel V-groove MOS device

Abstract: A short-channel V-groove MOS transistor is provided having laterally disposed source, drain, gate dielectric on the same face of a lightly p-doped substrate. Using ion implantation, a heavily doped vertical channel layer is symmetrically provided below and between the drain and the source in the substrate and being self-aligned to the gate which is formed in the V-groove by a silicon dioxide layer and a conductor layer. Appropriate leads contact the gate conductor, the drain and the source. Such transistor can be incorporated in an integrated circuit to form an inverter circuit with a lateral depletion-mode V-MOS as a load transistor.

Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit

Abstract: A low resistance crossunder (interconnect) for n-channel, silicon gate integrated circuits, particularly useful where shallow source and drain regions are employed. The crossunder is formed in the substrate from a doped polycrystalline silicon layer which contacts the substrate at the site of the crossunder. The crossunder is formed without substantial alterations to the standard process flow.

Semiconductor integrated circuit isolated through dielectric material and a method for manufacturing the same

Abstract: A semiconductor integrated circuit includes first and second island regions, surrounded by a bottomed dishlike dielectric layer formed on one side of a support body. A MOS transistor element is formed in the first island region, whose gate region is located at the bottom side of the island region. The gate electrode is connected to a bottom portion of the second island region, which is used as a gate electrode contact region, in the support body using a interconnection lead. There is a method for manufacturing the above device.

Field effect transistors

Abstract: A field effect transistor includes a thin silicon layer formed on a sapphire substrate and having source, gate and drain regions. A buried layer of the same conductivity type as that of the gate region and a higher impurity concentration than that of the gate region at the lower portion of a junction between the source and gate regions.

Radiation Dose Due to Electron-Gun Metallization Systems

Abstract: Electron beam evaporation is often selected as a method for depositing the gate metal for metal-oxidesemiconductor (MOS) devices. X-rays generated by electron impact on the metal to be evaporated may produce damage in the gate oxide. Several experimenters have reported that radiation-hardened MOS devices metallized in electron-gun systems appear to degrade at a faster rate than devices fabricated identically except for the metallization technique used. In order to examine ways of minimizing the damage introduced by electron beam systems and to develop a basis for understanding the physical phenomena observed, the physics of the x-ray energy deposition during the metallization process was explored. Details of the calculational procedure, the data necessary to calculate the x-ray absorbed dose in the oxide layer due to the electron-gun deposition of aluminum and chromium, and the calculations are presented. The results of experimental measurements of the x-ray dose are included for comparison. The implications of the results including the differences in the radiation susceptibility of MOS devices prepared with different gate metals are discussed.

P+ Silicon integrated circuit interconnection lines

Abstract: An improved interconnecting line for an integrated circuit comprising a P+ silicon island having an optional first layer of silicon dioxide or a like material thereon and a second layer of silicon nitride or a like material adjacent the first layer, is provided. The line may be manufactured by improvements in the standard P channel MOS or MNOS processing method wherein the line is formed concomitantly with the island upon definition of the silicon. The line may be subsequently coated with silicon dioxide during formation of a gate oxide for a MNOS device and then coated with silicon nitride.

Dual-gate schottky barrier gate fet having an intermediate electrode and a method of making same

Abstract: A dual-gate Schottky barrier gate field effect transistor is provided with an intermediate electrode between a first and a second gate electrode. This intermediate electrode forms an ohmic contact with a semiconductor substrate of the transistor. The transistor is produced by etching a first film formed on a planar surface of the substrate by the use of a pair of mask pieces to leave a pair of gate electrodes narrower than the mask pieces and projecting a metal capable of forming an ohmic contact with the semiconductor towards the planar surface perpendicularly thereof. The projected metal provides source and drain electrode on both sides of the gate electrode pair and an intermediate electrode between the gate electrodes. The intermediate electrode may be left floating during operation.

Gate protection device for MOS circuits

Abstract: The specification describes an integrated device for the input protection of MOS circuits. It consists of an MOS capacitor formed by the thinning of a section of the input gate dielectric, SiO2, and the thinning of an adjoining section of the gate metal, Al. An incoming pulse of static charge with high amplitude and short duration will break down the thinned dielectric of the capacitor before breaking down the relatively thick portion of the gate dielectric. Since the metal over the thin dielectric is also relatively thin, it evaporates from the vicinity of the fault by the generated Joule heat immediately following the breakdown. Thus, the breakdown is self healed and can be repeated many times without damaging the circuit.

Method of making integrated circuit MOS capacitor using implanted region to change threshold

Abstract: An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. The lower plate consists of a region which is implanted by an ion beam to produce a depleted region. This device has a constant capacitance regardless of gate voltage in normal operating logic levels.

Gate assist turn-off, amplifying gate thyristor and a package assembly therefor

Abstract: A conventional amplifying gate thyristor is provided with gate assist turn-off capability by a package assembly. The package assembly comprises an encapsulation means adapted for packaging therein the amplifying gate thyristor, said encapsulation means including a locator means for aligning and supporting a gate contact adapted to make ohmic contact with a gate electrode of the amplifying gate thyristor and for aligning and supporting a diode relative to said gate electrode. A diode is disposed in a semiconductor body having cathode and anode regions forming a PN junction therebetween and adjoining opposed major surfaces of said semiconductor body, respectively. The diode is fastened to said locator means with said cathode region thereof making ohmic contact with said gate contact and said anode region thereof making ohmic contact with an anode electrode affixed on a major surface of said semiconductor body and adapted to make ohmic contact with a floating electrode of the amplifying gate thyristor.

Dielectric and interface-state measurements of metal-spin-on-oxide-silicon capacitors

Abstract: Spin-on oxide refers to a thin film of silicon dioxide deposited from an alcohol solution applied by spinning to the surface of the semiconductor wafer. The dielectric properties of the oxide have been studied by C-V measurement and interface-state density has been measured using the quasistatic and AC conductance techniques.

Self aligned gate for di-CMOS

Abstract: A process for fabricating complementary metal oxide semiconductors including doping to determine threshold voltage of a first conductivity channel device with second conductivity type impurities, counter-doping to determine the threshold voltage of a second conductivity channel device with second conductivity impurities, forming gate oxide, forming metal gate, and forming source and drain regions using the metal gate as a self-aligned mask. Preferably, the doping steps are performed using ion implantation and photoresist mask.

Dual gate MNOS transistor

Abstract: A dual gate MNOS memory transistor is disclosed The transistor includes drain and source regions of a first conductivity type formed in a substrate of a second conductivity type The region of the substrate between the drain and source regions forms the channel of the transistor First and second insulating layers forming a charged trapping structure overlie the channel region A first gate having a width less than the width of the channel overlies the central portion of the channel region A second gate, insulated from the first gate, overlies the first gate and the remainder of the channel region The threshold voltage of the transistor is shifted by selectively biasing the gates and the substrate High and low threshold voltage states are used to represent the two values of a digital signal

Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

Abstract: A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a self-registering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation. The method also includes the provision for controlling the removal of insulation over the gate electrode wherever desired without seriously degrading the insulation over other parts of the structure. The disclosed method further relates to fabricating an integrated circuit containing FETs having a self-registered electrical connection between the gate electrode and the metallic interconnection line, the gate electrode self-aligned with respect to the source and drain regions, and wherein FETs of the integrated circuit have: a channel region; a gate insulator; an electrically conductive gate electrode; source and drain regions; thick insulation over the source and drain and over the gate electrode except in the contact areas; field isolation or field shield regions between FETs of the integrated circuit; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line.

Compact, two-phase charge-coupled-device structure utilizing multiple layers of conductive material

Abstract: An improved charge-coupled-device gate structure utilizes three depositions of electrically conductive material to form electrodes, thereby allowing fabrication of two-phase CCD gate structures occupying less wafer surface area and operating at faster speeds than conventional charge-coupled-device gate structures.