Showing papers on "Gate oxide published in 1990"

Silicon-on-insulator 'gate-all-around device'

Abstract: Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >

Comments on "The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors" [with reply]

Abstract: For original article by B.S. Doyle et al. see ibid., vol.37, p.1869-76, (Aug. 1990). In the above-titled paper the principal damage caused to n-MOSFETs during stress at low gate biases is claimed to be neutral electron trap generation in the gate oxide. These traps can supposedly be filled by injected electrons, when the transistor is biased at large drain and gate biases. When the generated electron traps are filled with electrons, a large degradation of current characteristics is observed. The commenters argue that no experimental evidence can be found to confirm this hypothesis. Using the data presented by Doyle et al. and in other studies the commenters show that the generation of neutral traps by injected holes is negligible. Neutral electron trap generation can, however, occur in MOSFETs when large oxide fields occur during operation. In reply, Doyle et al. argue that their normalization technique is correct, while that of the commenters leads to inconsistent results. After discussing several other points, they conclude that electron traps are created during channel hot-hole injection and must be taken into consideration in hot carrier lifetime estimates under AC conditions. >

Method of fabricating an high-performance insulated-gate field-effect transistor

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Self-aligned overlap MOSFET and method of fabrication

Abstract: A high speed submicron transistor which exhibits a high immunity to hot electron degradation and is viable for VLSI manufacturing. An inner gate member is formed on a p type substrate. A first source region and a first drain region are disposed in the p type substrate in alignment with the inner gate member for forming a lightly doped region. A conductive spacer is formed adjacent to and is coupled to each side of the inner gate member on the gate oxide layer for forming a gate member which overlaps the lightly doped region. A second source region and a second drain region are disposed in the first source region and first drain regions, respectively, self-aligned with the outer edges of the conductive spacers to form source and drain contact areas.

Quantum effects in Si n-MOS inversion layer at high substrate concentration

Abstract: The charge distribution at the semiconductgor-insulator interface is calculated for electrons by solving Schrodinger's and Poisson's equations self-consistently for particles obeying Fermi-Dirac statistics at 300 K. The results are applied to carriers in the channel of a crystalline MOSFET with the (100) axis perpendicular to the gate oxide. The inversion charge density calculated quantum mechanically is smaller than that calculated classically. This affects the shift of the subthreshold curves. The shift is larger at higher substrate impurity concentrations, and is especially pronounced at more than 10 17 cm −3 , which is the concentration used in recent MOS devices. The shift is as large as 0.18 V when the substrate impurity concentration is 8.5 × 10 17 cm −3 . Comparisons with measurement are also shown and it agrees well with quantum mechanical calculations. The inversion layer depth is compared, and a new efficient method is derived by transferring the quantum mechanical effect into the classical calculation. The results of this new method agree well with the quantum mechanical calculations and with the measurements.

Projecting gate oxide reliability and optimizing reliability screens

Abstract: The effect of time-dependent stress voltage and temperature on the reliability of thin SiO/sub 2/ films is incorporated in a quantitative defect-induced breakdown model. Based on this model, design curves which can be used along with a breakdown voltage distribution for an oxide technology to determine optimal burn-in conditions are presented. The tradeoff between improved reliability and lower burn-in yield for different gate oxide technologies can also be examined quantitatively using the model. >

Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof

Abstract: The EEPROM has the selection device in series with the memory device having a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 A to 1000 A of gate oxide, an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 40 A to 150 A of tunnel dielectric, and a control gate disposed over and insulated from the floating gate. The improvement in the proposed version of the memory device in the EEPROM is that the tunnel dielectric area is very small and is self aligned to the floating gate.

MOS device for long-term learning

Abstract: A semiconductor structure for long-term learning includes an n-type silicon substrate having a p-well region formed therein. An n-type region is formed within the well region. A polysilicon floating gate is separated from the surface of the silicon substrate by a gate oxide and is positioned above the well region. One edge of the polysilicon floating gate is aligned with the edge of the n-type region within the well region such that the polysilicon floating gate does not appreciably overly the n-type region. The substrate, the well, and the n-type region, respectively, form the emitter, base, and collector of a bipolar transistor.

Gate adjusted resonant tunnel diode device and method of manufacture

Abstract: A gated resonant tunneling diode has a semiconductor mesa formed on a semiconductor substrate, a tunneling barrier layer between the mesa and the substrate, and a gate layered over the substrate about the mesa and aligned in close proximity to the tunneling barrier layer. A control voltage on the gate laterally constricts a potential well in the tunneling barrier to control the electrical size of a channel within which tunnelling occurs across the tunneling barrier layer. Preferably the gate and the tunneling layer are disposed at the base of the mesa, and the gate makes a rectifying Schottky junction in connection with the tunneling barrier layer. The device is constructed using an anisotropic etch to form the mesa with an undercut wall and a top portion overhanging the undercut wall, and a nonconformal deposition of gate material to align the gate with the top portion of the mesa.

Floating gate memory cell and device

Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

Fabrication of self-aligned, t-gate hemt

Abstract: A generally T-shaped gate is formed by electron beam irradiation of a multilevel resist structure on a substrate. The resist structure has an upper layer which is more sensitive to the electron beam than a lower layer thereof. A generally T-shaped opening is formed in the resist structure by etching of the irradiated areas. An electrically conductive metal is deposited to fill the opening and thereby form a T-shaped gate on the substrate. After the resist layer structure and metal deposited thereon is removed, a masking layer is formed on the substrate around the gate, having an opening therethrough which is aligned with and wider than the cross section of the gate, and defining first and second lateral spacings between opposite extremities of the cross section and adjacent edges of the opening. Deposition of an electrically conductive metal forms source and drain metallizations on the substrate on areas underlying the first and lateral spacings respectively. The metallizations are self-aligned to the gate and separated therefrom by the masking effect of the gate during the metal deposition. The gate may have an asymmetrical top section which provides a larger spacing between the gate and drain metallization than between the gate and source metallization to increase the breakdown voltage of the device. Insulative oxide sidewalls may be formed on the gate.

Investigation on the oxide field dependence of hole trapping and interface state generation in SiO2 layers using homogeneous nonavalanche injection of holes

Abstract: Homogeneous injection of holes into the gate oxide of metal‐oxide‐semiconductor (MOS) devices was obtained using p‐channel MOS transistors under illumination conditions. Because gate hole currents could be measured the dependence of the hole trapping on the oxide electric field and on the energy of the holes at the injection point could be investigated. In contrast to results recently reported for electron injection no evidence for the generation of traps during hole injection was found. Only a small dependence of the capture cross section on the oxide field was observed. The study of the interface state generation during hole injection at various fields revealed that the amount of interface states directly generated by the injected holes is less than 5% of the number of trapped holes. For longer times a transformation process occurs and a correlation is found between the detrapping of holes and the generation of interface states.

Selective germanium deposition on silicon and resulting structures

Abstract: The invention is a method of selectively forming contacts on ultra shallow source and drain junctions. The method comprises forming a gate structure that defines a gate on a silicon substrate, portions of which are covered with a layer of silicon dioxide while the portions adjacent the gate form a silicon surface. The gate structure includes a surface material upon which germanium will not deposit at a temperature that is otherwise high enough to cause germanium to deposit from a germanium containing gas onto a silicon surface, but that is lower than the temperature at which germanium will deposit on the gate surface material. A source and drain are formed in the silicon substrate in the portions adjacent the gate by adding dopant atoms and in which the source and drain are separated by an active region of the silicon substrate defined by the gate structure. The substrate is then exposed to a germanium containing gas at a temperature high enough to cause the germanium to deposit from the germanium containing gas into the silicon surface but lower than the temperature at which the germanium will deposit on the gate structure surface material. The result is self-aligned germanium contacts to the source and the drain. The method can further comprise selectively depositing a metal on the germanium and annealing the deposit to form a germanide compound from the reaction between the deposited germanium and the deposited metal.

A reliable bi-polarity write/erase technology in flash EEPROMs

Abstract: The authors describe a technology for scaling down the flash EEPROM cell, which has a conventional self-aligned double poly-Si stacked structure. It is clarified experimentally that a flash memory cell written and erased by Fowler-Nordheim (F-N) tunneling has ten times the retention time of the conventional cell, which is written by channel-hot-electron (CHE) injection and erased by F-N tunneling. This difference of data retentivity between these two write/erase (W/E) technologies is due to decreasing the thin gate oxide leakage current by bi-polarity F-N tunneling stress. This improvement in data retention becomes more pronounced as the gate oxide thickness decreases. Therefore, a bipolarity F-N tunneling WE technology, which enables a flash EEPROM cell to scale down its oxide thickness, shows promise as a key technology for realizing 16 Mb flash EEPROMs and beyond. >

Polycide gate FET with salicide

Abstract: A process for forming a field-effect-transistor structure upon a silicon substrate includes the steps of sequentially depositing a polysilicon layer and a refractory metal silicide layer over a gate oxide and heating the same to form a polycide gate structure. After etching the polycide composite layer to define the gate, spacer oxide layers are formed to cover the lateral edges of the gate structure, and a transition metal layer is deposited over the bare polycide composite layer and the surrounding bare source and drain diffused silicon regions. The deposited transition metal layer is annealed to react with the polycide in the gate structure and thereby lower the sheet resistance of the gate. The transition metal also reacts with the source and drain regions to form silicides for lowering the sheet resistance of the source and drain regions. Unreacted transition metal is removed from the upper surface of the substrate, and subsequent glass deposition, contact opening, and metalization may be performed in the usual manner.

Three-dimensional memory cell with integral select transistor

Abstract: A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the source and drain has both horizontal and vertical regions. The cell also includes a floating gate, which is completely surrounded with insulation, and a control gate which is insulated above and extends over the floating gate. The control gate is also insulated above and extends over the vertical portion of the channel within the slot. This allows the second gate member to regulate the current flowing in the vertical portion of the channel; that is, the second gate member and the vertical channel section form an integral select device.

A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistors

Abstract: A physical model considering the effects of grain boundaries on the turn-on behavior of polysilicon thin-film transistors (poly-Si TFTs) is presented. Along the channel, the formation of the potential barrier near the grain boundary is proposed to account for the low transconductance and high turn-on voltage of TFTs. The barrier height is expressed in terms of channel doping, gate oxide thickness, grain size, and external gate as well as drain biases. Drain bias results in an asymmetric potential barrier and introduces more carrier injection from the lowered barrier side. It is shown that this consideration is very important for characterizing the saturation region under large drain-bias conditions. On the basis of the developed potential barrier model, the I-V characteristics are described by the interfacial-layer thermionic-diffusion model. Thin-film transistors on polycrystalline silicon with a coplanar structure were fabricated for testing. Comparisons show excellent agreement between the developed model and the experimental data. >

The transduction of host‐guest interactions into electronic signals by molecular systems

Abstract: Synthetic receptor molecules that selectively bind charged guests can store chemical information. The transduction of this information into electronic signals connects the chemical and electronic domains. Field effect transistors (FETs) are attractive transducing elements because these microdevices are able to register and amplify chemical changes at the gate oxide surface of the semiconductor chip. Integration of molecular receptors and field effect transistors into one chemical system gives a device that can communicate-changes of substrate activities in aqueous solution. Simulations of a system in which the receptor molecules are directly attached to the FET gate oxide indicate serious limitations with respect to sensitivity, dynamic range and extreme requirements for complex stability. Therefore we have concentrated on the integration of covalently attached thin membranes. The problem of the thermodynamically ill-defined oxidemembrane ipterface has been solved by applying a covalently linked hydrophilic polyhydroxyethylmethacrylate (polyHEMA) gel between the sensing membrane and the silylated gate oxide. A buffered aqueous electrolyte solution in the hydrogel renders the surface potential at the gate oxide constant via the dissociation equilibrium of the residual silanol groups. The subsequent attachment of a polysiloxane membrane that has the required dielectric constant, glass transition temperature Tg, and receptor molecule, provides a stable chemical system that transduces the complexation of cationic species into electronic signals (CHEMFET). The response to changing K concentrations in a solution of 0.1 M NaCl is fast (<1 sec) and linear in the concentration range of 10-5-1.0 M (55-58 mV /decade). A reference FET (REFET) based on the same technology is obtained when the intrinsic sensitivity to changes in ion concentration is eliminated by the addition of 2.10-5 mol g-1 of didodecyldimethyl ammonium bromide to the ACE membrane. Differential measurements with a REFET/CHEMFET combination showed excellent linear K response over long periods of time. All chemical reactions used are compatible with planar IC technology and allow fabrication on wafer scale.

High voltage MOS transistor having shielded crossover path for a high voltage connection bus

Abstract: An MOS transistor having a closed layout plan in which the drain is laterally surrounded by the source and gate and having an extended charge carrier drift zone between the gate and drain, thereby achieving high reverse breakdown voltage An oxide or other dielectric layer is provided on the surface of the drift zone, and on such layer between the gate and drain electrodes a crossover path is formed by a succession of unconnected narrow conductive strips extending transversely to such path and having a dielectric coating thereon A high voltage external connection bus for the drain electrode traverses such crossover path and extends through a gap formed by a disjuncture in the gate and source electrodes Since the length of each of the conductive strips greatly exceeds the width of the connection bus, the coupling capacitance between each strip and such bus in much less than the coupling capacitance between such strip and the underlying portion of the drift zone The drift zone can thereby be effectively shielded from the electric field of the connection bus by including a sufficient number of conductive strips in the crossover path traversed by the connection bus

Method of making a three-dimensional memory cell with integral select transistor

Abstract: A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the source and drain has both horizontal and vertical regions. The cell also includes a floating gate, which is completely surrounded with insulation, and a control gate which is insulated above and extends over the floating gate. The control gate is also insulated above and extends over the vertical portion of the channel within the slot. This allows the second gate member to regulate the current flowing in the vertical portion of the channel; that is, the second gate member and the vertical channel section form an integral select device.

Self-aligned gate process for fabricating field emitter arrays

Abstract: Conical field emitter elements are formed on a surface of a substrate after which a layer of metal is deposited on top of the substrate surface and over the field emitter elements. A layer of oxide is then deposited over the metal layer. Another layer of metal is deposited over the layer of oxide to form a gate metal layer. A layer of photoresist is then deposited over the gate metal layer. The layer of photoresist is then plasma etched in an oxygen atmosphere to cause portions of the photoresist above respective field emitter elements to be removed and provide self-aligned holes in the photoresist over each of the field emitter elements. The size of the holes may be controlled by appropriately controlling process parameter, including plasma etching time and power and/or initial photoresist thickness. The exposed gate metal layer is etched using the layer of photoresist as a mask. The photoresist layer is removed, and the layer of oxide is etched to expose the field emitter elements. Another oxide layer and an anode metal layer also may be formed over the gate metal layer to produce a self-aligned triode structure.

Electrically programmable non-volatile memory device and manufacturing method thereof

Abstract: A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Thickness limitations of SiO/sub 2/ gate dielectrics for MOS ULSI

Abstract: The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si/sub 3/N/sub 4/ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current. >

A comprehensive study on p/sup +/ polysilicon-gate MOSFET's instability with fluorine incorporation

Abstract: It is reported that fluorine can jeopardize p/sup +/-gate devices under moderate annealing temperatures. MOSFETs with BF/sub 2/ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10/sup 12/ cm/sup -2/) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p/sup +/-gate revealed that the long gate-length device had abnormal abrupt turn-on I/sub d/-V/sub g/ characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I/sub d/-V/sub g/ characteristics associated with long-gate-length p/sup +/-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p/sup +/-gate devices is presented. The incorporation of fluorine in the p/sup +/ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states. >

Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

Abstract: Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E/sub c/L/sub eff/, where E/sub c/ is the critical electric field necessary to cause carrier velocity saturation and L/sub eff/ is the effective channel length, is introduced. Experimental results confirmed that 1.1E/sub c/L/sub eff/ predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 mu m). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E/sub c/L/sub eff/ can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6- mu m channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E/sub c/L/sub eff/. >

Silicon-on-insulator 'gate-all-around' MOS device

Abstract: The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described. >

Semiconductor memory which is protected from erasure by light shields

Abstract: A nonvolatile semiconductor memory device having memory cells in which a control gate is stacked on a floating gate through an insulating film. The memory device has redundant memory cells so as to compensate defective memory cells and a transistor to select the redundant memory cells and the redundant memory cells and the transistor to select the redundant memory cells are formed by a nonvolatile memory transistor. The transistor to select the redundant memory cells has a structure in which the upper surface and side walls of the floating gate are covered by a control gate or a structure in which the floating gate and control gate are covered by a light shielding film and an antireflection film formed under the light shielding film. In a nonvolatile semiconductor memory device having memory cells of a structure in which a control gate is stacked on a floating gate through an insulating film, a phosphosilicate glass film is formed on side walls of the floating gate and the control gate and a silicon nitride film and an arseno-silicate glass film or boro-phospho-silicide glass film are sequentially formed so as to cover the control gate.

Process for creating two thicknesses of gate oxide within a dynamic random access memory

Abstract: A process for creating two thicknesses or gate oxide within a dynamic random memory. The process begins by thermally growing a first layer of gate oxide on a silicon substrate. This first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is then removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. The resultant oxided layer, which comprises multiple-thickness components, is used as a pad oxide layer during a conventional LOCOS operation. Peripheral driver transistors are construction on top of a thin layer of gate oxide so as to optimize their performance, whereas, cell access transistors are constructed on top of a thicker layer of gate oxide so as to minimize row line capacitance. A net increase in row line access speed is thus obtained.

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

Abstract: The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple degraded MOSFET model. It was found that the number of the generated interface states is defined uniquely by the amount of peak substrate current, independently from the gate-oxide thickness. The major cause of the smaller degradation in the thinner gate-oxide device is smaller mobility degradation due to the generated interface states. The degraded mobility was measured and formulated. The smaller mobility degradation is explained by the difference between the vertical electric field dependence of the Coulomb scattering term and that of the phonon term under the inversion condition. The effect of a larger channel conductance, due to the larger inversion charges for the thinner gate-oxide device, is the secondary cause for the smaller degradation. >

Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate-films

Abstract: The boron penetration effect was compared for p/sup +/ poly gate PMOSFETs with pure oxide gates and nitrided oxide gates. For a gate thickness of 6.5 nm, reduced boron dosage and rapid thermal processing solve the problem of boron penetration in the pure oxide case. However, when the film thickness is less than 6.5 nm, only a nitrided oxide film can solve the problem. From the results of EDX analysis in nitrided oxide films, it was found that nitrogen build-up at the interface is small and that a nitrogen concentration of only a few percent leads to complete suppression of boron penetration down to the 2 nm range of film thickness. Excellent characteristics in 2.6 nm nitrided oxide gate p-MOSFETs, free from boron penetration effects, were demonstrated. >