Showing papers on "Low-dropout regulator published in 2007"

Full On-Chip CMOS Low-Dropout Voltage Regulator

Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

Abstract: This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

High-efficiency dc/dc voltage converter including capacitive switching pre-converter and up inductive switching post-regulator

Abstract: A DC/DC converter includes a pre-converter stage, which may include a charge pump, and a post-regulator stage, which may include a Buck converter. The duty factor of the post-regulator stage is controlled by a feedback path that extends from the output terminal of the DC/DC converter to an input terminal in the post-regulator stage. The pre-converter steps the input DC voltage up or down by a positive or negative integral or fractional value, and the post-regulator steps the voltage down by a variable amount depending on the duty factor at which the post-regulator is driven. The converter overcomes the problems of noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios.

Current regulator for modulating brightness levels of solid state lighting

Abstract: An exemplary embodiment provides a current regulator for controlling variable brightness levels for solid state lighting. The current regulator is couplable to a phase-modulating switch, such as a dimmer switch, which is coupled to an AC line voltage. An exemplary current regulator includes a rectifier; a switching power supply providing a first current; an impedance matching circuit; and a controller. The impedance matching circuit is adapted to provide a second current through the phase-modulating switch when a magnitude of the first current is below a first predetermined threshold, such as a holding current of a triac of the phase-modulating switch. The controller is adapted to determine a root-mean-square (RMS) voltage level provided by the phase-modulating switch from the AC line voltage and to determine a duty cycle for pulse-width current modulation by the switching power supply in response to the comparison of the RMS voltage level to a nominal voltage level.

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

Abstract: A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm2. The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV VDO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.

A Low-Dropout Regulator for SoC With $Q$ -Reduction

Abstract: A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.

Algorithms for Controlling Both the DC Boost and AC Output Voltage of Z-Source Inverter

Abstract: This paper aims to achieve good performance for both the dc boost and the ac output voltage control of the Z-source inverter (ZSI). The algorithm to control linearly the capacitor voltage is suggested in order to improve the transient response for dc boost control of the ZSI. The peak value of the ac output voltage is used to control exactly the ac output voltage to its desired level. A modified space vector pulsewidth modulation scheme is applied to control the shoot-through time for boosting dc voltage. The proposed algorithms are verified with simulation and experiment with a 32-bit digital signal processor.

A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance

Abstract: A 0.6mum 1.8V 5mA Miller-compensated SoC LDO regulator uses 60pF of capacitance to achieve a worst-case power-supply rejection of -27dB over 50MHz. The entire regulator is shielded from fluctuations in the supply using an NMOS cascode that is biased using a charge pump, voltage reference, and RC filters to maintain low dropout. The RC filter establishes a stable bias for the cascode without a significant impact on the efficiency or bandwidth of the LDO regulator.

Constant On-Time Regulator With Internal Ripple Generation and Improved Output Voltage Accuracy

Abstract: A buck switching regulator formed on an integrated circuit receives an input voltage and provides a switching output voltage on a switch output node using a constant on-time, variable off-time feedback control loop. The buck switching regulator includes an amplifier comparing a feedback voltage to a reference voltage and generating an output voltage on an output terminal, a first capacitor and a first resistor connected in series between the switch output node and the output terminal of the amplifier, and a second capacitor coupled between the DC output voltage node and the output terminal of the amplifier. The first capacitor and the first resistor generate a ripple voltage signal which is injected onto the output terminal of the amplifier for use in the constant on-time, variable off-time feedback control scheme. The magnitude of the ripple voltage signal is a function of the capacitance value of the second capacitor.

Current driven memory cells having enhanced current and enhanced current symmetry

Abstract: A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on.

Charge balance control methods for asymmetrical cascade multilevel converters

Abstract: Modulation strategies for multilevel converters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of DC voltage levels. This results in the average current injection and hence the net power drawn from the multiple DC voltages to be unmatched and time varying. Therefore, the DC voltage sources are unregulated, requiring corrective control action to incorporated. In this paper, first a new method is proposed for determination of DC voltage source levels of asymmetric cascade multilevel converters. Then four modulation strategies are proposed for DC power balance realization for asymmetrical multilevel converters expectation of the first unit. All of the expressed theoretical results are confirmed by simulation and experimental results.

Switching voltage regulator with low current trickle mode

Abstract: For load currents greater than a threshold current, the voltage regulator operates in a conventional manner by fully turning on and off one or more switching transistors (16) at a duty cycle necessary to maintain the output voltage a regulated voltage. Upon a load current below a threshold being detected (76), a controller stops the switching of the transistor(s) and applies a reduced drive signal (44) to the high side transistor so as to apply a constant trickle current to the load. Unnecessary components are shut down to save power (42). When the output voltage falls below a threshold (46), the normal switching routine is resumed to recharge the regulator's output capacitor (28) to a certain level, and the regulator once again enters the light load current mode. By not completely shutting down the transistors at light load currents, as in done in a conventional intermittent-operation mode, there is lower power loss by less frequent switching of the transistor(s).

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Abstract: Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.

A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

Abstract: A 10b 205MS/S 1mm2 ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1Vpp single-ended input at 205MS/S. The core ADC power consumption is 40mW from a 1V non-regulated supply.

Low-dropout voltage regulator with a voltage slew rate efficient transient response boost circuit

Abstract: A low-dropout (LDO) voltage regulator for generating an output voltage is disclosed. The voltage regulator includes a startup circuit, a curvature corrected bandgap circuit, an error amplifier, a metal oxide semiconductor (MOS) pass device and a voltage slew rate efficient transient response boost circuit. The MOS pass device has a gate node which is coupled to the output of the error amplifier, and a drain node for generating the output voltage. The voltage slew rate efficient transient response boost circuit applies a voltage to the gate node of the MOS pass device to accelerate the response time of the error amplifier in enabling the LDO voltage regulator to reach its final regulated output voltage when an output voltage drop occurs in the LDO voltage regulator.

Constant on-time regulator with increased maximum duty cycle

Abstract: A buck switching regulator receives an input voltage and provides a switching output voltage on a switch output node using a minimum on-time, variable off-time feedback control loop. The buck switching regulator includes an on-time control circuit for generating a first signal for turning off the high-side switch at the expiration of a first on-time duration or at the expiration of a maximum on-time. The first on-time duration is at least a minimum on-time and is allowed to expand to a maximum on-time when the feedback voltage remains less than a reference voltage. The maximum on-time includes a first maximum on-time and a second, extended maximum on-time. The second maximum on-time is applied when a minimum off-time was used for the high-side switch during the previous switching cycle. In another embodiment, the second maximum on-time is applied only when the switching regulator is not being current limited.

Buck-Boost Switching Voltage Regulator

Abstract: A buck-boost switching regulator includes two buck switches and two boost switches. Two ramp voltages VY and VY are generated. The voltage VY is compared to a voltage VEA 1 that is proportional to the output of the switching regulator. This defines the duty cycle of the two buck switches. The voltage VX is compared to a voltage VEA 2 that is inversely proportional to the output of the switching regulator. This defines the duty cycle of the two boost switches. The regulator seamlessly transitions between Buck, Boost and Buck-Boost modes depending on input and output conditions.

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters

Abstract: Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated linear regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the linear regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, linear regulator occupies 0.03 mm2 for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work

Circuit and method for predicting a valley timing for a voltage across a switching device

Abstract: Disclosed are circuits and methods for use in a control circuit of a switching mode power supply for turning on a switching device in the switching mode power supply when the voltage across the switching device is at a minimum. A voltage detector is provided for detecting the voltage across the switching device to produce a detection voltage which is a function of the voltage across the switching device, and circuit arrangement is used to predict a valley timing for the voltage across the switching device by evaluating the time period that the detection voltage falls down from a first threshold to a second threshold.

Fast low dropout voltage regulator circuit

Abstract: A voltage regulator includes first and second closed-loop amplifiers and a N-type transistor. The first amplifier receives a first reference voltage and a feedback voltage. The second amplifier is responsive to the first amplifier and to the regulated output voltage of the regulator. Both amplifiers are biased by a biasing voltage. The second amplifier has a bandwidth greater than the bandwidth of the first amplifier and a gain smaller that the gain of the first amplifier. The N-type transistor has a first terminal responsive to the output of the second amplifier, a second terminal that receives the input voltage being regulated, and a third terminal that supplies the regulated output voltage. The feedback voltage is generating by dividing the regulated output voltage. An optional fixed or dynamically biased current source biases the first terminal of the N-type transistor. The voltage regulator optionally includes an overshoot correction circuit.

Polar transmitter having a dynamically controlled voltage regulator and method for operating same

Abstract: A supply voltage controlled power amplifier includes a power amplifier, a closed power control loop configured to generate a power control signal, and a voltage regulator coupled to the power control loop, the voltage regulator including a first regulator stage, a second regulator stage, and a peak detector, wherein an output of the second regulator stage is applied as a feedback signal to the first regulator stage and wherein an output of the first regulator stage is decreased to a level consistent with an output of the power amplifier and an additional operating buffer amount

Implementation of output floating scheme for hv charge pumps

Abstract: According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.

Method and apparatus to compensate for supply voltage variations in a PWM-based voltage regulator

Abstract: A feed-forward correction circuit in a PWM controller adjusts an error signal inversely with respect to a supply voltage for a switching voltage regulator to quickly compensate for changes or transients in the supply voltage. The adjusted error signal is provided to a PWM comparator to control a duty cycle of an output signal. The switching voltage regulator can be a DC-to-DC converter or a DC-to-AC converter, and the output signal is used to generate one or more driving signals to control semiconductor switches in the switching voltage regulator. The feed-forward correction circuit uses an offset compensation technique or a translinear circuit to maintain a substantially inverse product relationship between the supply voltage and the duty cycle of the output signal, thereby reducing overshoots and undershoots in a regulated output voltage of the switching voltage regulator.

A Novel Topology for Photovoltaic Series Connected DC/DC Converter with High Efficiency Under Wide Load Range

Abstract: The paper proposes a new topology for photovoltaic DC/DC converter with high efficiency under wide input voltage range is proposed. Photovoltaic DC/DC is a very crucial part of power conditioning system(PCS). Considering that output characteristic of photovoltaic cell has wide voltage range, depending on the operating conditions of photovoltaic cell, the DC/DC converter also needs to have wide input voltage range to regulate the constant output voltage. In addition, a high rated voltage of power switch (MOSFET) for DC/DC converter is necessary in order to be compatible with the high maximum output voltage of photovoltaic cell's maximum output voltage. Also photovoltaic power conditioning system should have a high efficiency under operation condition. To satisfy PV PCS condition series connected non-isolated DC/DC converter topology is proposed. This paper examines the proposed topology employing four modules and shows that it dramatically enhances the energy efficiency from low load to high load condition by reducing the required power level for DC/DC converter by one-third of conventional DC/DC converter. A case of 20 kW prototype as the PV DC/DC converter is introduced to experimentally verify the proposed topology.

Soft-start circuit and method for low-dropout voltage regulators

Abstract: A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET. A current limit circuit is configured to control the power FET to limit the current through it when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value. At start-up, control unit provides a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally in value at respective predetermined incremental times during a predetermined time interval.

Control circuit and method for maintaining high efficiency in switching regulator

Abstract: A high efficiency control circuit for operating a switching regulator is provided. The switching regulator can regulate an output voltage no matter the input voltage is higher, lower, or close to the output voltage. The switching regulator has first, second, third and fourth switches. The control circuit can operate the switching regulator in buck mode, boost mode, or buck-boost mode. In a buck-boost mode, the control logic drives the four switches in an efficiency sequence for reducing energy consumption during the switch transition, on the other side, resistive loss owing to the energy transfer phase is also minimized. Furthermore, the invention is capable of control duty cycle limitation to fit the consideration of the linearity of the converter.

Voltage regulator output stage with low voltage MOS devices

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

Compensating NMOS LDO regulator using auxiliary amplifier

Abstract: An LDO (low dropout) regulator including a pass transistor having a first electrode coupled to produce an output voltage of the LDO regulator, a control electrode, and a second electrode coupled to receive an input voltage of the LDO regulator. An error amplifier has a first input coupled to a first reference voltage and an output coupled to the gate control electrode of the pass transistor. A first feedback circuit has an input coupled to the first electrode of the pass transistor and an output producing a first feedback voltage coupled to a second input of the error amplifier. The auxiliary amplifier has a first input coupled to a second reference voltage and an output coupled to the output of the error amplifier. A second feedback circuit has an input coupled to the output of the auxiliary amplifier and an output producing a second feedback voltage coupled to a second input of the auxiliary amplifier. The auxiliary feedback loop is used to take over control of the feedback in the LDO regulator at high frequencies.

Power supply circuit and battery device

Abstract: A power supply circuit with low noise and low power consumption and a battery device using the power supply circuit. If a voltage VDD is higher than a prescribed voltage, a charge pump circuit 140 A is operated in “½ mode” (a step-down ratio of “2”), steps down the voltage VDD, and outputs an intermediate voltage VCPO. Since the voltage VDD is stepped down, the intermediate voltage VCPO being input into a first LDO 135 is about half the case where no step-down is carried out, and the power being consumed in a MOS transistor Q 11 (FIG. 3 ) of the first LDO 135 is greatly reduced. Therefore, the increase in power consumption of the first LDO 135 due to a voltage increase in the voltage VDD can be suppressed. Also, since the heat sink of the first LDO 135 can be reduced in size or omitted by the suppression of power consumption, the size and weight of the device can be reduced.

AC Voltage Regulator Based on the AC-AC Buck-Boost Converter

Abstract: The study and implementation of an ac voltage regulator is presented in this paper. Traditionally an ac voltage regulator is made with a transformer tap changer or with an ac-ac converter based on buck topologies, recently the developments in ac-ac converter makes feasible the implementation of voltage regulator with other topologies. In this paper is analyzed an ac voltage regulator based on the ac-ac buck-boost converter, the commutation trouble is solved with two inductors. The controller used permits to obtain a good dynamic response for large input voltage variations. The operation and brief analysis is included. Simulations and experimental results are presented.