Showing papers on "Physical design published in 1996"

Performing optical proximity correction with the aid of design rule checkers

Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s

Abstract: In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.

Microelectronic Circuit Design

Abstract: This preview guide presents the first 10 chapters of the our new title by Richard Jaeger: Microelectronic Circuit Design. This cutting edge new text develops a comprehensive understanding of the basic techniques of modern electronic circuit design, analog and digital, discrete and integrated. Digital electronics has evolved to be an extremely important area of circuit design, but it is included almost as an after-thought in the majority of introductory electronics texts. This book presents a much more balanced coverage of analog and digital circuits. The writing integrates the author's extensive industrial backround in precision analog and digital design with his many years of experience in the classroom.

Module placement on BSG-structure and IC layout applications

Abstract: A new method of packing the rectangles (modules) is presented with applications to IC layout design. It is based on the bounded-sliceline grid (BSG) structure. The BSG dissects the plane into rooms associated with binary relations ``right-to''and ``above'' such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of modules on the BSG, followed by physical realization BSG-PACK. A simulated annealing searches for a good packing of all packings by changing the assignments. Experiments showed that hundreds of rectangles are easily packed in a small rectangle area (chip) with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Remarkable examples are: the chip is not necessarily rectangle, L-shaped modules and modules which are allowed to partially overlap each other can be handled.

A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits

Abstract: This paper describes a top-down, constraint-driven design methodology for analog integrated circuits. Some of the tools that support this methodology are described. These include behavioral simulation tools, tools for physical assembly, and module generators. Finally, examples of behavioral simulation with optimization and physical assembly are provided to better illustrate the methodology and its integration with the tool set.

An Introduction To VLSI Physical Design

Abstract: From the Publisher: This text treats the physical design of very large scale integrated circuits gradually and systematically. It examines the design problem and the design process with the aim of evaluating the efficiency of automatic design systems through algorithmic analysis. The layout problem is viewed as a collection of sub-problems which can be individually solved efficiently and then effectively combined. Initially,the text reviews VLSI technology and then examines layout rules and cell generation techniques.

Concurrent electronic circuit design and implementation

Abstract: A system for providing real time design feedback to a user of a data processing system for designing an electronic circuit includes a display system, a graphical, textual or mixed user input process which displays user input on the display system for designing an electronic circuit, and an implementation process with which generates an implementation of the electronic circuit in for example a field programmable gate array Feedback is provided by monitoring the user input process to detect a change in the design of the electronic circuit Upon detection of a change, information about the change is forwarded to the implementation process The implementation process is executed as a background process to the user input process, in response to the change to produce implementation data on an incremental basis Information about the implementation data is displayed on the display system as feedback to the user during the design process Analysis of the implementation data produces information indicating the speed of operation of the generated implementation, information indicating the size of the generated implementation, or information consisting of a particular type of integrated circuit device on which the implementation should be made The system provides immediate implementation feedback allowing an interactive design entry process for computer software based integrated circuit design

Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies

Abstract: Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC design process. In this tutorial, we look at the last decade's worth of progress on analog circuit synthesis and layout tools. We focus on the frontend and backend of analog and mixed-signal IC design flows. The tutorial summarizes the problems for which viable solutions are emerging, and those which are still unsolved.

Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

Abstract: Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delay-insensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute low-skew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic supports the cyclic, deterministic behavior of the synchronous design paradigm. This permits the designer to rely chiefly on current experience and CAD tools to create phased logic systems. Marked graph theory is used as a framework for governing the interaction of phased logic gates that operate directly on Level-Encoded two-phase Dual-Rail (LEDR) signals. A synthesis algorithm is developed for converting clocked systems to phased logic systems and is applied to benchmark examples. Performance results indicate that phased logic tends to be tolerant of logic delay imbalances and has predictable worst-case timing behavior. Although phased logic requires additional circuitry, it has the potential to shorten the design cycle by reducing timing complexities.

Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system

Abstract: An initial placement of cells for an integrated circuit chip is decomposed into a hierarchial order of groups of cells. The groups are routed simultaneously using parallel processors, and the results are recomposed to provide a global routing that provides a detailed mapping of cell interconnect congestion in the placement. Areas of high congestion are identified, and a congestion reduction algorithm is applied using the parallel processors to alter the placement in these areas simultaneously. The overall fitness of the placement is then computed, and if it has not attained a predetermined value, the steps of identifying congested areas and applying the congestion reduction algorithm to these areas are repeated. The cumulative error created by altering the placement without repeating the global routing is estimated, and if it exceeds a predetermined value, the global routing is also repeated.

S-matrix oriented CAD-tool for simulating complex integrated optical circuits

Abstract: A design tool for simulation of complex integrated optical circuits, based on a professional microwave design system has been developed. Implementation of a number of components is described and a simulation example of an add-drop node using a 4/spl times/4 phased array is presented.

Apparatus and method for management of integrated circuit layout verification processes

Abstract: An apparatus and method for managing data obtained during the Design Rule Check (DRC) and Layout versus Schematic (LVS) verification procedures executed during the design of an integrated circuit. The apparatus is a data processing system which includes a database containing information regarding the schematics and layouts of the cells of an integrated circuit. The system accesses the database upon the completion of a DRC or LVS operation and queries the user as to whether the cell should be marked as successfully passing the appropriate verification procedure. A user is also able to access a report generating module to inspect the verification status of a cell in the IC design and generate a report showing the status of the verification procedures for each cell, organized according to one of several criteria.

Automated generation of megacells in an integrated circuit design system

Abstract: A computer-base system and method automate the generation of megacells in the design and layout of integrated circuits. The preferred method utilizes an automatic design generator having a user interface which receives design requirements for a megacell or other complex integrated circuit design. A megacell processor receives the design requirements for the megacell and retrieves relevant megacell implementations from a megacell library. Stored megacell benchmarks are then retrieved from a megacell benchmark memory and applied to corresponding megacells to determine which of the various implementations optimally satisfies the user design requirements. Once the optimal megacell implementation is selected, the megacell processor produces a logic design consisting of a net list and a physical design consisting of design directives which are then used to place and route the megacell as a finished layout. Once the layout is completed, the finished layout is simulated and tested and test results from the finished layout simulation are then fed back to the automatic design generator where the megacell benchmark memory is updated.

A CMOS analog circuit for Gaussian functions

Abstract: A simple CMOS analog circuit that performs the Gaussian function for classification applications is introduced. Combining the exponential characteristics of MOS transistors in weak inversion and the square characteristics in strong inversion the function is built. Design constraints and mismatch effects are discussed, as well as the layout optimization. The circuit has been designed in a SOI technology and manufactured. Good experimental results are obtained which shows that the circuit is suitable to be included as a building block of an IC to perform classification tasks or other possible applications.

Design for manufacturability in submicron domain

Abstract: Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) trade-offs. Yield and cost models needed to analyze these trade-offs are explained as well.

High performance method of and system for selecting one of a plurality of ic chips while requiring minimal select lines

Abstract: A circuit is provided for selecting one of plurality of integrated circuit chips with a minimum number of chip select signal lines. A first embodiment includes a plurality of paired address lines; each line in each pair provides a logical complementary signal. Only a selected one of the lines of each pair is coupled to integrated circuit. Each of the integrated circuits is coupled to a unique combination of these selected lines of the pairs. In a second embodiment a select signal is clocked by a controller from one of the integrated circuits to the next in a fashion similar to a shift register. Once the select signal is present in the desired integrated circuit, the controller then provides an enable signal to all the integrated circuits which enables only that desired integrated circuit. In yet another embodiment, the address lines are also used as chip select signal lines, one address line for each integrated circuit. A Chip_select_clock_enable line is used to toggle the chip select signal to the desired device. In a preferred embodiment, a unique value is stored in a register on each integrated circuit. A controller places the unique value of a desired integrated circuit onto a bus. A comparator in each integrated circuit determines which chip has been selected. The controller then provides a chip select signal to activate the desired integrated circuit.

Method and apparatus for performing drive strength adjust optimization in a circuit design

Abstract: A method and apparatus for efficiently optimizing a circuit design by substituting identified cells within the circuit design with logically equivalent cells having different drive strengths. The present invention eliminates the need to update the design database and to place and route the circuit design during each design iteration. Rather, an improved extraction tool is provided which incorporates a cell substitution list, and updates the RC file therefrom. The updated RC file is used by the timing analysis tool to determine if the updated design will meet the design specification. After the design meets the design specification, a final place and route may be performed.

Integrated circuit layout

Abstract: The invention quickly produces a dense layout for an integrated circuit that enables a smaller die to be used to implement the integrated circuit than would otherwise be the case, resulting in a desirable size reduction in the final packaged integrated circuit. The invention combines routing space estimation and adjustment (a technique similar to channel-based global routing) with area-based detailed routing, resulting in an approach that provides the benefits of both channel-based and area-based layout techniques while minimizing the disadvantages of those techniques.

Method and apparatus for voltage regulation within an integrated circuit package

Abstract: An integrated circuit package comprising an integrated circuit device and a voltage converter circuit both embedded within the package. The voltage converter circuit is configured to convert a standard supply voltage to an operating voltage as required by the integrated circuit device. Also, discrete embedded capacitors may be included to capacitively couple power and ground connections of the integrated circuit device and thus reduce voltage variations during operation of the integrated circuit device. The integrated circuit may package include one or more layers. One or more discrete components or integrated circuits are mounted to one or more layers within the package. Internal conductors on one or more of the layers are configured to connect the components forming the voltage converter circuit. Internal conductors also form connections to the integrated circuit device. The integrated circuit device and voltage converter circuit may be coated with an encapsulant for added protection. The integrated circuit package with embedded voltage converter may be manufactured with processes similar to those used for traditional integrated circuit packages and printed circuit board assemblies.

Anti-fuse programming path

Abstract: A programmable circuit in an integrated circuit provides a programmed signal, which is based on the state of a first node. An anti-fuse includes a first terminal coupled to the first node and a second terminal coupled to a programming bus. An anti-fuse programming pad is coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit. The state of the programmed signal can be used to replace a primary circuit element in the integrated circuit, such a row or column of memory cells in a memory integrated circuit, with a redundant circuit element.

Analog layout using ALAS

Abstract: An analog layout assistant (ALAS!) is presented that automatically generates common-centroid, interdigitated device pairs and passive components. The user inputs a minimum of input parameters and has the ability to interactively alter the parameters of the program. The program can be used in conjunction with any layout editor that imports CalTech Intermediate Format (CIF) layouts and is platform and technology independent.

Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof

Abstract: First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.

Method and apparatus for incremntally optimizing a circuit design

Abstract: A method and apparatus for incrementally optimizing a circuit design. The present invention provides an iterative EDA process that only requires the optimization, placement and routing of the actual changes made during a each design iteration, and leaves the remainder of the circuit design in a fixed state.

Apparatus and method for the automatic determination of a standard library height within an integrated circuit design

Abstract: The present invention relates to a method (100, 150, 200) and associated data processing system (250) for determining a standard cell height within an integrated circuit design. A plurality of cell types, each cell type including a plurality of cell structures are received (102). Then, weighting values are received, one for each cell type (104). Expected intercell connection densities are preferably also received. Various target cell heights are processed with the plurality of cell types, the weighting values, and the expected intercell connection densities to generate a standard cell height (106). The standard cell height used with the integrated circuit design produces an optimized integrated circuit area, preferably a minimum area. The present invention includes a method (200) and system (250) for selecting an optimized standard cell height that, when used with a place-and-route tool to generate a physical design file (204) produces an optimized physical integrated circuit design. A method of manufacture (300) is also included.

Method and apparatus for optimizing a circuit design having multi-paths therein

Abstract: A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.

Parametric tuning of an integrated circuit after fabrication

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit. For example, by selecting the appropriate load resistance and/or capacitance of the tunable circuit, the rise/fall time of the target circuit is tuned for compatibility with respect to the other portions of the IC or system. The tunable circuit of the present invention advantageously lends itself to post-fabrication correction of design or fabrication problems, thereby increasing the potential yield rate. In addition, the tunable circuit can be tested under different operating conditions in a non-destructive manner without the need for another time-consuming and costly IC fabrication cycle. Other advantages include the ability to selectively operate target circuit(s) of the IC at a higher speed under ideal conditions and at a lower speed under hostile conditions.

Neural network applications in device and subcircuit modelling for circuit simulation

Abstract: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

Predictive capacitance layout method for integrated circuits

Abstract: A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.

Statistical computer-aided design for microwave circuits

Abstract: A useful methodology for microwave circuit design is presented. A statistical technique known as Design of Experiments is used in conjunction with computer-aided design (CAD) tools to obtain simple mathematical expressions for circuit responses. The response models can then be used to quantify response trade-offs, optimize designs, and minimize circuit variations. The use of this methodology puts the designer's intelligence back into design optimization while making "designing for circuit manufacturability" a more systematic and straightforward process. The method improves the design process, circuit performance, and manufacturability. Two design examples are presented in context to the new design methodology.

Design planning for high-performance ASICs

Abstract: Design planning is emerging as a solution to some of the most difficult challenges of the deep-submicron VLSI design era. Reducing design turnaround time for extremely large designs with ever-increasing clock speeds, while ensuring first-pass implementation success, is exhausting the capabilities of traditional design tools. To solve this problem, we have designed and implemented a hierarchical design planning system that consists of a tightly integrated set of design and analysis tools. The integrated run-time environment, with its rich set of hierarchical, timing-driven design planning and implementation functions, provides an advanced platform for realizing a variety of ASIC and custom methodologies. One of the system's particular strengths is its tight integration with an incremental, static timing engine that assists in achieving timing closure in high-performance designs. The design planner is in production use at IBM internal and at external ASIC design centers.