Showing papers on "Resist published in 1994"

Introduction to microlithography

Abstract: An Introduction to Lithography The Lithographic Process: The Physics Organic Resist Materials Resist Processing Plasma Etching

Method of etching an oxide layer

Abstract: A method of etching an oxide layer is disclosed. First, a resist layer is formed on an oxide layer on a substrate. Next, a photosensitive layer is formed on the oxide layer and patterned to expose regions of the oxide layer to be removed. The exposed regions may overlie a nitride layer, and may overlie a structure such as a polysilicon gate. The etch is performed such that polymer deposits on the photosensitive layer, thus eliminating interactions between the photosensitive layer and the plasma. In this way, a simple etch process allows for good control of the etch, resulting in reduced aspect ratio dependent etch effects, high oxide:nitride selectivity, and good wall angle profile control.

Method for manufacturing semiconductor device

Abstract: PURPOSE:To manufacture a semiconductor device with a small junction-leakage current and a large current-driving capability. CONSTITUTION:In the state wherein a tungsten polyside film 17 of the gate electrode of a semiconductor device is covered with an SiO2 film, an impurity is injected into a polycrystalline Si film 45, and the impurity is diffused to an Si substrate 11 to form diffusion layers 26, 32. Thereafter, the polycrystalline Si film 45 is covered with a resist 46 to remove the SiO2 film, and then, impurity ions are implanted into the tungsten polyside film 17. Since a formation of the diffusion layers 26, 32 and the introduction of the impurity into the gate electrode are performed separately from each other, the condition of the heat treatment of the introduced impurity can be set independently of others. Therefore, the diffusion layers 26, 32 having favorable junction characteristics can be formed, and the lowering of the concentration of the impurity of the gate electrode is prevented, and further, the decrease of the gate capacity of the semiconductor device and the increase of its threshold voltage can be prevented.

Low voltage electron beam lithography in self‐assembled ultrathin films with the scanning tunneling microscope

Abstract: With a scanning tunneling microscope (STM) operating in vacuum, we have studied the lithographic patterning of self‐assembling organosilane monolayer resist films. Where the organic group is benzyl chloride, the resist layer can be patterned with electrons down to 4 eV in energy. The patterned films have been used as templates for the electroless plating of thin Ni films. Linewidths down to ∼20 nm have been observed in scanning electron micrographs of the plated films. Still smaller features are observed in STM images of the exposed organosilane films.

Generation of electrochemically deposited metal patterns by means of electron beam (nano)lithography of self‐assembled monolayer resists

Abstract: Submicron metal patterns have been produced by galvanic deposition in openings in a monolayer resist generated by electron beam (e‐beam) lithography. The monolayer resist is a self‐assembled docosanethiol (C22H45SH) layer adsorbed on gold. Proper removal of the thiol requires an e‐beam dose of 10–100 mC cm−2. The positive resist pattern was used to selectively deposit galvanic copper. The size of the Cu patterns is affected by the galvanic deposition time and the CuSO4 concentration in the electrolyte solution. The smallest Cu patterns produced were about 75 nm in width.

Method of manufacturing semiconductor device

Abstract: PURPOSE:To make an insulating film flat with high precision by a method wherein a film to be patterned which has an undercut and resist to be reversely patterned are formed on the insulating film and the resist on the insulating film and the insulating film are etched at the same time. CONSTITUTION:First and second resists 6, 8 are mutually reverse sensitivity and also when these resists 6, 8 are patterned, the identical exposing mask 7 is used with the identical position relationship. Therefore, the first resist 6 is used as a mask and is patterned, and the second resist 8 has reversed patterns with respect to that of the film to be patterned. Accordingly, when the second resist 8 and the insulating film 4 for filling steps are etched at the same time, an insulating film 4 is etched from a projecting part exposed from the second resist 8 and a recessed part coated with the second resist 8 is etched after the second resist 8 is completely removed by etching. Thus, the flatting of the insulating film 4 can be carried out with good controllability and high precision.

Method for forming a fine resist pattern

Abstract: A method for forming a fine resist pattern by exposing comprising the steps of: (i) forming a resist layer on a semiconductor substrate; (ii) forming a phase shifting pattern in an upper portion of the resist layer, the phase-sifting pattern having a tapered edge corresponding to a portion to which formation of an objective fine resist pattern is not desired; (iii) exposing the entire surface of the semiconductor substrate including the phase-shifting pattern; and (iv) forming a fine resist pattern below an outline except for the tapered edge of the phase-shifting pattern.

Electron beam lithography with monolayers of alkylthiols and alkylsiloxanes

Abstract: Self‐assembled monolayers have been modified with focused electron beams of energy 1–50 keV and scanning tunneling microscopy (STM) based lithography with energies of ∼10 eV. Modifications ∼15 nm in size have been formed by STM and ∼25 nm in size by 50 keV beams. The fact that these materials work as self‐developing electron beam resists is demonstrated by both atomic force microscopy imaging and pattern transfer using conventional wet etchants. Patterns have been transferred to silicon substrates to a depth of ≳120 nm with a multistep wet etching process. The mechanism of electron beam modification has also been explored to better design future monolayer processes.

Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS

Abstract: The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.

Isolation structure using liquid phase oxide deposition

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

Scanning Probe Lithography. 2. Selective Chemical Vapor Deposition of Copper into Scanning Tunneling Microscope-Defined Patterns

Abstract: : A scanning tunneling microscope (STM) has been used to define features having critical dimensions ranging from 0.05 to 5.0 micrometer within a self-assembled monolayer resist of octadecylmercaptan, HS(CH2)17CH3, confined to a Au (111) surface. Low temperature chemical vapor deposition (CVD) methods were used to metalize the STM-patterned surface with Cu. At substrate temperatures near 120 deg C, the Cu CVD precursor, hexafluoroacetylacetonatocopper(I)-(1,5- cyclooctadiene), disproportionates to deposit Cu on the STM-etched portion of the substrate, but not on the unetched methyl-terminated monolayer resist surface. At substrate temperatures significantly above 120 deg C the degree of selectivity is reduced, probably as a result of thermal desorption of the organomercaptan monolayer.

Manufacture of thin-film transistor

Abstract: PURPOSE: To make it possible to simplify the manufacturing steps of an offset region in a submicron or micron order by performing the etching step of a gate electrode, the impurity implantation step and the re-etching step under the same mask. CONSTITUTION: After resist, photosensitive polyimide 106 and the like are patterned by photolithograhy, a gate electrode 107a is etched by a CDE method or the like so that the angle of θ 1 =25°C is formed. Thereafter, ions are implanted, and phosphorus is implanted by an ion doping method, without peeling the resist, the polyimide and the like. Furthermore, under the intact used state, wherein the etching is performed by the CDE method, this part is used as the mask in anisotropy etching by an RIE method without peeling the resist, the polyimide and the like. When the gate electrode is etched again at the taper angle of θ 2 =87 degrees by the RIE method, an offset region of 110 of about 600nm and an LDD region 109 of about 460nm can be formed. COPYRIGHT: (C)1995,JPO

Nanometer scale patterning and oxidation of silicon surfaces with an ultrahigh vacuum scanning tunneling microscope

Abstract: Nanoscale patterning of the Si(100)‐2×1 monohydride surface has been achieved by using an ultrahigh vacuum (UHV) scanning tunneling microscope(STM) to selectively desorb the hydrogen passivation. Hydrogen passivation on silicon represents one of the simplest possible resist systems for nanolithography experiments. After preparing high quality H‐passivated surfaces in the UHV chamber, patterning is achieved by operating the STM in field emission. The field emitted electrons stimulate the desorption of molecular hydrogen, restoring clean Si(100)‐2×1 in the patterned area. This depassivation mechanism seems to be related to the electron kinetic energy for patterning at higher voltages and the electron current for low voltage patterning. The patterned linewidth varies linearly with the applied tip bias achieving a minimum of <10 A at −4.5 V. The dependence of linewidth on electron dose is also studied. For positive tip biases up to 10 V no patterning occurs. The restoration of clean Si(100)‐2×1 is suggestive of selective area chemical modifications. This possibility has been explored by exposing the patternedsurface to oxygen and ammonia. For the oxygen case, initial oxidation of the patterned area is observed. Ammonia dosing, on the other hand, repassivates the surface in a manner different from that of atomic hydrogen. In both cases the pattern resolution is retained and the surrounding H‐passivated areas remain unaffected by the dosing.

Proximity-dispensing high-throughput low-consumption resist coating device

Abstract: A minimal amount of waste in liquid resist material is achieved by dispensing through small openings at close proximity to the substrate. An airtight substrate chamber as well as airtight sealing of dispensing assembly and airtight sealing of the space that does not have to be opened for substrate loading and unloading, are used to facilitate a uniform and planarized coating after a high-speed spin off of excess resist.

Low temperature anisotropic ashing of resist for semiconductor fabrication

Abstract: This invention encompasses using anisotropic plasma at a low temperature to strip resist from a semiconductor wafer. A semiconductor wafer 10 is placed in a reactor 26 which contains an oxygen plasma source 28. The oxygen plasma source 28 emits oxygen plasma 32 which is drawn towards the biased wafer 10, exposing the resist layer 22 of the wafer to anisotropic oxygen plasma. A sensor 30 detects when the ashing of the resist is complete, and then the plasma source is turned off. Advantages of the invention include the ability to remove resist from wafers without damaging polymeric dielectric layers, which are sensitive to the harsh effects of traditional resist removal methods. With the present invention, very little damage occurs to the material on the sidewalls of vias.

Resist hardening process having improved thermal stability

Abstract: The present invention is directed to a method of hardening a photoresist formed on a patterned layer during photolithograpy, without causing undesirable shrinkage of the resist features. The patterned layer is disposed on a semiconductor substrate, and the photoresist layer is disposed on the patterned layer in a conventional manner. The photoresist layer is irradiated and developed in a conventional manner to have the desired pattern formed therein. The larger features of the developed photoresist layer are irradiated without heat to thereby harden these features, without irradiating the smaller features. The hardening may be performed by screening the smaller features from the radiation applied to the photoresist layer, or by scanning a beam across only the larger features. The radiation may be UV light or an electron beam. Alternatively, all of the features of the photoresist may be hardened by exposure to a basic atmosphere immediately before, during or immediately after irradiation with UV light. In both cases, the features are hardened without shrinkage. After the features are hardened, the photoresist and patterned layer are etched in a conventional manner to transfer the pattern to the patterned layer.

Method for three-dimensional control of solubility properties of resist layers

Abstract: An electron beam exposure method for controlling the solubility of resist layers used in a variety of lithography processes, to permit removal of the resist material from selected positions and depths in the resist. By controlling the energy of a uniform electron beam impinging on the resist, the method selects a resist depth for applying a dose of electrons, the effect of which is to change the solubility properties of the resist material at the selected positions and depths. Subsequent removal of unwanted portions of the resist produces desired resist wall slope and edge profiles in the developed patterns in photoresist. One embodiment of the invention uses the same basic method to produce three-dimensional structures in the resist material, including bridge-like structures in which lower layers are removed from beneath intact upper layers. In a variant of this embodiment, the same technique is used to form a three-dimensional mold in the resist material, and then three-dimensional structures of another material, such as metal are formed by filling the mold.

A new patterning process concept for large-area transistor circuit fabrication without using an optical mask aligner

Abstract: A new concept to produce large thin film transistor liquid crystal displays (TFT-LCD's) without using an optical mask aligner is proposed which emphasizes patterning technology. Some experimental thin film transistors (TFT's) are fabricated according to the concept and operated like conventional transistors fabricated by using an optical mask aligner. The concept includes improvement of printing technology and development of a double-layer resist method. The latter method employs a printed ink pattern and a photoresist. This prevents contamination of thin films by metal impurities which affect electrical characteristics of the TFT's. A special gravure offset printing technology is proposed, composed of a large thixotropy valued UV ink, and a fine, precision etched glass intaglio. The experimental TFT's, with a designed minimum gate length of 10 /spl mu/m, have comparable electric characteristics to those of conventional poly-Si TFT's. >

Coating apparatus and method

Abstract: A coating apparatus comprises a chuck on which a semiconductor wafer is adhered, a resist liquid supplying system for supplying a resist liquid to the semiconductor wafer, a motor for rotating the semiconductor wafer, thereby spreading the resist liquid over the semiconductor wafer, and a plate, on which the semiconductor wafer is placed, for creating a temperature distribution on the semiconductor wafer.

Method of etching a pattern on a substrate using a scanning probe microscope

Abstract: A scanning probe microscope is used to pattern a layer of resist, and the pattern is transferred to a substrate. First, an underlayer formed of, for example, polyimide and a top layer formed of, for example, amorphous silicon are deposited on the substrate. A pattern is formed on the top layer using the tip of the cantilever in a scanning probe microscope. The pattern may consist of an oxide formed by an electric field at the cantilever tip. The top layer is then etched using the pattern as a mask and using an etchant that is selective against the underlayer. The underlayer is then etched using an etchant that is selective against the top layer and substrate. The substrate is etched with an etchant that removes the top layer but is selective against the underlayer. Finally, the underlayer is removed.

Method of removing resist mask and a method of manufacturing semiconductor device

Abstract: The present invention relates to a method of manufacturing a semiconductor device including a process of removing a photoresist mask or a photosensitive polyimide mask remaining after implanting impurity ions into a semiconductor layer or the like, and has an object to prevent generation of oxides of impurities and photoresist explosion and arranging it so that no residue remains. The present invention comprises the steps of forming a mask composed of photosensitive organic matter on a layer, implanting impurity ions into the layer through the mask, and removing the mask through processing including three steps of: exposing the mask to a plasma activated gas containing hydrogen, exposing to the mask to a plasma activated gas containing oxygen, and exposing the mask to a solution containing nitric acid under conditions sufficient to dissolve alumina which had formed on the mask during exposure of the mask to oxygen.

The effect of an organic base in chemically amplified resist on patterning characteristics using KrF lithography

Abstract: A new resist system composed of an SEPR chemically amplified (CA) positive resist and an N-methyl pyrrolidone (NMP) organic base has been developed for KrF excimer laser lithography. Using 0.30-µ m l&s patterns formed with KrF stepper, we studied the effect of contamination from substrate films of plasma chemical vapor deposition silicon dioxide (P-CVD SiO2), low pressure CVD silicon nitride (LP-CVD Si3N4) and reactive sputtered titanium nitride (TiN), and of airborne contamination under the condition of an 8-ppb of ammonia. The results clarify the new resist system reduces the effect of substrate film as well as airborne contamination. The new resist system enables us to form fine patterns on any substrate and attains more than one hour post-exposure delay without overcoat and undercoat films.

Multilayer resist pattern forming method

Abstract: A multilayer resist pattern forming method patterns a lower resist layer formed over the stepped surface of a workpiece by a high-speed, highly anisotropic ion mode etching using an intermediate pattern formed by etching an intermediate layer formed by a high-density plasma CVD process as a substantial etching mask. The intermediate layer formed by the high-density plasma CVD process has a dense film quality and highly resistant to ion bombardment. Therefore, the intermediate resist pattern is neither thinned nor contracted and, consequently, the lower resist pattern can be formed precisely in conformity with the design rule. Since the high-density plasma promotes interaction between source gases to enable the intermediate layer to be formed at a comparatively low processing temperature, which prevents damaging the lower resist layer by heat.

50‐nm x‐ray lithography using synchrotron radiation

Abstract: A technology of proximity x‐ray lithography has been developed to replicate patterns of sub‐100‐nm feature size using synchrotron radiation. Process modeling has been done in advance in order to optimize the mask absorber thickness. It is shown that with tungsten absorber, a 0.3 μm thickness is the most desirable for 50 nm linewidth processing. Masks compatible with a Karl Suss stepper have been fabricated using 50 keV electron‐beam lithography and reactive ion etching techniques. As a result, well‐defined 50‐nm‐wide isolated W lines and small gratings of period down to 100 nm have been fabricated. Then they have been replicated under proximity condition using Super ACO synchrotron radiation. We present details of a replication procedure with gap settings down to 5 μm and show how sub‐100 nm structures can be 1:1 printed into both poly (methylmethacrylate) (PMMA) and (8.5%) MAA/PMMA resists. Finally, the results are analyzed in terms of a scaling rule to evaluate the resolution limit as a function of proximity gap using a synchrotron source.

New mask evaluation tool: the microlithography simulation microscope aerial image measurement system

Abstract: The Zeiss MSM100 microlithography simulation microscope can evaluate phase shift and conventional photolithographic masks. In this paper we discuss the MSM design, its operation, image capture and analysis methods, and typical applications. The tool's unique optical system captures `through focus' images of a mask for a selected NA, sigma, and wavelength, thus paralleling the characteristics of a particular optical stepper. The MSM operates at i-line (365 nm) and DUV (248 nm) wavelengths, and handles commonly used 5 or 6 inch reticles. The images obtained are optically equivalent to that incident on resist, but are highly magnified so that they may be recorded using a DUV CCD camera. Typically, features of interest are recorded as a through focus series; image intensity is digitized. Application to the assessment of defect printability, both before and after repair, is presented. Masks have been analyzed to predicted CD values which are in good agreement with subsequent resist work. Unconventional illumination schemes have been studied.

Optimizing proximity correction for wafer fabrication processes

Abstract: A key requirement for any proximity correction method is the ability to accurately predictproximity effects for any given circuit configuration. In this paper we present amethodology for characterizing proximity effects from measurements taken on aprocessed wafer. The characterization will determine what types of effects are present,which effects can be corrected, and it will quantify behavior parameters for a generalizedproximity error model.Keywords: proximity correction, process characterization, lithography, compensation 2. Introduction In general, an integrated circuit layout pattern specifies the planar dimensions needed onwafer structures. The image is transferred through several tooling and fabrication steps,including the mask, projection lithography, resist, and etch. Deviations can be introducedat each step, distorting the image by the time it is embodied in silicon. Distortions thataffect dimensions and shapes of wafer features are called "proximity effects."When the mechanisms that cause such distortions are stable, it is possible to predict themand modify the layout image to compensate for the expected deviations. Until recently,for the most part, such corrections have been limited to constant size adjustments onpattern features to correct an average bias introduced by the wafer process. At advanceddesign rules, 0.35 mm and smaller, proximity effects consume a substantial portion of thedimensional tolerances required on the wafer, in spite of sizing compensations. Modernproximity correction techniques provide detailed compensation shapes based on specificpattern configurations.

Chemically amplified resist composition

Abstract: Positive-tone and negative-tone chemically amplified resist compositions comprising: (a-1) a blocked resin, (a-2) a combination of an alkali-soluble resin and a dissolution controlling agents, or (a-3) a combination of an alkali-soluble resin and a crosslinking agent, (b) a photoacid generator, and (c) specific kinds of solvents. The both positive-tone and negative-tone resist compositions exhibits superior sensitivity, high resolution capability, and excellent storage stability, and can be excellently applied especially to large sized substrates by spincoating for producing excellently shaped patterns by irradiation. The compositions can be used with advantage as a chemically amplified resist for the manufacture of semiconductor devices or integrated circuits (ICs).

Process for fabricating a device

Abstract: The invention is directed to a process for fabricating an integrated circuit. An imaging layer is deposited on a substrate. The imaging layer is an energy sensitive resist material. The energy sensitive resist material contains moieties that preferentially bind to refractory material. A latent image of a pattern is introduced into the imaging layer by patternwise exposing the imaging layer to energy. The patternwise exposure introduces a selectivity into the resist material that is exploited to bind refractory material preferentially to either the exposed resist material or the unexposed resist material, but not both. The refractory material forms an etch mask over the resist material to which it preferentially binds. This etch mask is then used to transfer a pattern that corresponds to the latent image into the substrate.

Proximity-compensated blazed transmission grating manufacture with direct-writing, electron-beam lithography

Abstract: Proximity-compensated, as well as uncompensated, blazed transmission gratings with periods of 4, 8, and 16 μm were manufactured with direct-writing, electron-beam lithography in positive resist. The compensated gratings performed better than the uncompensated ones. For the 4-μm compensated grating the measured diffraction efficiency was 67%. It was 35% for the uncompensated grating. The compensation was made by repeated convolutions in the spatial domain with the electron-beam point spread function. We determined this function by retrieving the phase from the measured diffraction pattern of the uncompensated gratings.