Showing papers on "Silicon on insulator published in 1989"

Short-channel effect in fully depleted SOI MOSFETs

Abstract: The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness. >

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET

Abstract: A fully depleted lean channel transistor (DELTA) having a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported In the deep submicron region, selective oxidation is useful for achieving SOI isolation It provides a high-quality crystal and a Si-SiO/sub 2/ interface as good as those of conventional bulk single-crystal devices Using experiments and simulation, it was shown that the gate structure of DELTA has effective channel controllability and its vertical ultrathin ( >

Short-channel effects in SOI MOSFETs

Abstract: Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed. >

Analysis of conduction in fully depleted SOI MOSFETs

Abstract: The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction. >

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Abstract: Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-AA-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation. >

Three dimensional ICs, having four stacked active device layers

Abstract: The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interface buffer circuits, and a CMOS SRAM. Fabrication technologies for the four-layer-stacked 3-D IC are described. Laser beam recrystallization was carried out for the formation of three SOI (silicon-on-insulator) layers in the 3-D IC. Recrystallization without cracks in both SOI and vertical isolation layers was accomplished by adjusting laser annealing conditions. Microprobe Raman spectroscopy data indicated that a tensile stress of (3-6)*10/sup 9/ dyne/cm/sup 2/ was present in each SOI layer. Surface planarization of the vertical isolation layer was carried out with a combination of polystyrene spin coating and dry etching. An initial surface roughness of about 1.7 mu m was successfully reduced to less than 500 A, and the planarized surface did not interfere with either recrystallization or photolithography. NMOSFETs and PMOSFETs, fabricated in the four-layer-stacked 3-D IC, have been successfully operated. >

Characterization of front and back Si-SiO/sub 2/ interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

Abstract: It is shown that the charge-pumping technique can be successfully applied to SOI structures, directly providing important and reliable information about the quality of both front- and back-gate interfaces. The possibility of performing measurements on a transistor level makes direct correlation with other MOS characteristics and material parameters possible. In particular, the ability of this technique to perform measurements on thin-film transistors and to separate the information from front and back gates makes it indispensable for characterization of advanced SOI CMOS structures. Although the technique was demonstrated only on 5- mu m channel length devices, it has sufficient sensitivity to be applicable to transistors of micrometer and submicrometer dimensions. Charge-pumping measurements on laser-recrystallized SOI MOSFETs showed that the front interface is only slightly deteriorated compared to that of bulk MOSFET devices, while the back interface is of a substantially lower quality, with about 10 times higher interface trap densities. >

Near-intrinsic thin-film SOI FETS

Abstract: A submicrometer, near-intrinsic, thin-film, SOI complementary filed effect transistor structure is disclosed. The device is characterized by having a gate comprising material having a work function which approximates its Fermi level to the middle of the band gap of the channel material. Such devices display desirable transconductance, subthreshold slope and punch-through resistance.

Physical origin of negative differential resistance in SOI transistors

Abstract: From a two-dimensional solution of Laplace's equation it is shown that a significant increase in temperature occurs in the channel of SOI transistors due to the relatively poor thermal conductivity of the buried insulator. Based on this simulation an equation is derived which predicts that at small channel lengths the pinchoft point is shifted, an effect which is consistent with experimental observations. In addition, the positive 'kink' is reduced with increasing gate voltage and this effect, together with the negative differential resistance, can be explained by a temperature increase in the channel.

Model for CMOS/SOI single-event vulnerability

Abstract: A lumped-parameter model derived from transistor characterization data has been used in SPICE analyses to study and predict the single-event-upset thresholds for SIMOX SOI (separation by implantation of oxygen, silicon-on-insulator) SRAMs (static random-access memories) with a variety of cell designs. The modeling of CMOS/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure. Results indicate that, in the SOI devices investigated, single events simulate a localized bipolar response, even in devices with bodies electrically tied to active nodes. The bipolar response enhances the destabilizing effect of an ion event. The total current impulse contributing to upset can be significantly greater than that produced by direct ionization within the hit transistor, i.e., devices can be upset by ions that deposit less than the total charge required to initiate logic state reversal. In light of this, advanced CMOS/SOI-SOS logic with short channel lengths (and therefore significant parasitic bipolar gain) may exhibit critical LETs (linear energy transfers) lower than expected from simple scaling rules, and thinning of the active regions may not significantly reduce single-event rates in such CMOS/SOI digital circuits. >

Reduced defect density in silicon‐on‐insulator structures formed by oxygen implantation in two steps

Abstract: Up to now, the best quality silicon‐on‐insulator material formed by high‐dose oxygen ion implantation has been produced by conventional one step implantation and subsequent high‐temperature annealing. Nevertheless, it still contains structural defects: threading dislocations in the top silicon film and silicon islands inside the buried SiO2 layer. This letter presents a new method for producing silicon‐on‐insulator structures using sequences of oxygen ion implantation and high‐temperature annealing steps. The structures obtained using this method are nearly free from defects observable by electron microscopy. In particular, no threading dislocations could be observed and the density of silicon islands is reduced by several orders of magnitude. A mechanism of Si interstitial atoms migration is proposed to explain these observations in accordance with other studies.

Monolithic integration of silicon on insulator and gallium arsenide semiconductor technologies

Abstract: A semiconductor heterostructure includes separate, device quality regions of gallium arsenide and silicon layers on an insulating substrate such as aluminum oxide or silicon dioxide. The separate regions can be electrically isolated except for intended connections, permitting the fabrication of interrelated gallium arsenide and silicon semiconductor active devices on a single substrate. The device quality gallium arsenide is grown overlying the specially treated device quality silicon layer, by depositing a thin transition layer of gallium arsenide in low temperature growth, annealing it by solid phase epitaxy, and then depositing at a higher temperature a thicker epitaxial layer of gallium arsenide overlying the transition layer.

Silicon double-injection electro-optic modulator with insulated-gate and method of using same

Abstract: A double-injection transistor structure with an MOS gate is utilized as a guided-wave electro-optic phase modulator at infrared wavelengths in a silicon-on-insulator (SOI) waveguide. Cathode, gate and anode regions are integrated in the waveguide, longitudinally. The effective phase modulation is given by the voltage-variable overlap of the guided-mode optical field with carrier-induced local changes in the silicon refractive index. An electron-hole plasma is injected under the gate by cathode and anode. Using depletion-layer widening, the plasma channel width and mode overlap are controlled very rapidly by one or two low-power gate electrodes.

Thin-film SOI technology: the solution to many submicron CMOS problems

Abstract: The performances of thin-film SOI (silicon-on-insulator) MOSFETs and CMOS circuits are presented. Attention is given to the SOI material, device properties, and design and processing. It is noted that this technology is extremely attractive for deep-submicron applications because of such properties as improved subthreshold slope, reduced short-channel effects, reduced electric fields, increased transconductance, and better immunity to soft errors. Front-end CMOS processing of thin films of SOI is also considerably simpler than bulk device processing. The competitiveness of TFSOI technology on the CMOS market is discussed. >

Thick contacts for ultra-thin silicon on insulator films

Abstract: CMOS devices on SOI and a method for making such devices with ultra-thin Si channel regions and thick Si drain and source regions for good contact surfaces are described.

Epitaxial Lateral Overgrowth of Si by LPE with Sn Solution and Its Orientation Dependence

Abstract: A single crystal Si layer was grown over SiO2 film by epitaxial lateral overgrowth (ELO) using LPE, and the dependence of the ratio of the lateral to the vertical growth rates on crystal orientation was investigated. Sn was used as a solution, and it was found that the growth surface was flat and completely mirror like. The lateral growth had a singularity when the line seed was aligned in just the orientation, but it was almost constant when the orientation was varied around the orientation. The time dependence of the growth was investigated, and it was found that both the lateral width and the vertical thickness were approximately proportional to t1/2, and the volume of the growth was proportional to t0.9. Sirtl etch revealed that almost no etch pits were observable on the ELO layer. This result shows that ELO by LPE yields SOI films with an extremely good crystal quality.

Method of manufacturing a semiconductor device having an SOI structure using selectable etching

Abstract: The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body (1) having a buried insulating layer (7). Such a type of semiconductor device is known as a device of the SOI type. According to the invention, the starting material is a substrate (1) of monocrystalline semiconductor material with a top layer (2). Ions are implanted into a zone located under the top layer so that the zone becomes selectively etchable with respect to the remaining part of the substrate. The zone is then etched away, a cavity then being formed between the top layer (2) and the remaining part of the substrate (1). The cavity is filled at least in part with insulating material (7). By known techniques, semiconductor circuit elements can be provided in the top layer (2) thus disposed on the insulating layer (7).

An analytic model for thin SOI transistors

Abstract: A simple charge sheet model is shown to provide a surprisingly accurate approximation to the behavior of a long-channel FET fabricated in a silicon-on-insulator (SOI) structure with a very thin silicon film. Using this charge sheet model, an accurate calculation of the I-V characteristics of transistors fabricated in these thin films is derived. Included in the results is an expression for the threshold voltage which shows, among other things, that the threshold voltage of suitably designed transistors is only logarithmically dependent on the thickness of the silicon film. >

Method for producing a semiconductor device having a silicon-on-insulator structure

Abstract: A method for producing a semiconductor device having a silicon-on-insulator structure, includes the steps of depositing a first insulation film on a silicon substrate by a chemical vapor deposition process, patterning said first insulation film so as to be left in a silicon-on-insulator (SOI) element region, a portion of said silicon substrate having no first insulation film thereon being served as a bulk element region, depositing a polysilicon layer on an entire surface of said silicon substrate, patterning said polysilicon layer so as to be left on said patterned first insulation film, a patterned polysilicon layer being served as an active region, and simultaneously forming second and third insulation films for use in element insulation in said silicon substrate and said patterned polysilicon layer, respectively, by a local-oxidation-of-silicon (LOCOS) process, so that said bulk element region in surrounded by said second insulation film, and said SOI element region is surrounded by said third insulation film.

Heterostructures on silicon : one step further with silicon

Abstract: In the field of logic circuits in microelectronics, the leadership of silicon is now strongly established due to the achievement of its technology. Near unity yield of one million transistor chips on very large wafers (6 inches today, 8 inches tomorrow) are currently accomplished in industry. The superiority of silicon over other material can be summarized as follow: - The Si/Si0 interface is the most perfect passivating interface ever 2 obtained (less than 10" e y-I cm2 interface state density) - Silicon has a large thermal conductivity so that large crystals can be pulled. - Silicon is a hard material so that large wafers can be handled safely. - Silicon is thermally stable up to 1100 C so that numerous metallurgical operations (oxydation, diffusion, annealing ... ) can be achieved safely. - There is profusion of silicon on earth so that the base silicon wafer is cheap. Unfortunatly, there are fundamental limits that cannot be overcome in silicon due to material properties: laser action, infra-red detection, high mobility for instance. The development of new technologies of deposition and growth has opened new possibilities for silicon based structures. The well known properties of silicon can now be extended and properly used in mixed structures for areas such as opto-electronics, high-speed devices. This has been pioneered by the integration of a GaAs light emitting diode on a silicon based structure by an MIT group in 1985."

Low leakage silicon-on-insulator CMOS structure and method of making same

Abstract: A CMOS device is provided with a field shield region below one of the P and N channel MOS transistors, whereby the field shield region is formed to have the opposite conductivity of both the one MOS transistor it underlies, and of the substrate, thereby permitting the field shield region to be biased to a potential for turning off any anomalous back channel leakage current in the one MOS transistor, and also permitting the substrate to be biased to an opposite polarity for turning off such leakage current in the other MOS transistor.

Radiation hardened complementary transistor integrated circuits

Abstract: Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.

Interface characterization of silicon epitaxial lateral growth over existing SiO/sub 2/ for three-dimensional CMOS structures

Abstract: The silicon-silicon dioxide interface created by the epitaxial lateral growth of monocrystalline silicon (ELO) over existing thermally oxidized silicon was investigated using a novel device structure This structure is proposed as the basic building block of technology for the fabrication of locally restricted three-dimensional integrated CMOS circuits, as well as advanced bipolar devices Results are reported from the investigation of the surface states of this silicon-on-insulator (SOI) interface It is demonstrated that these interfaces can exhibit characteristics comparable to those interfaces created by the thermal oxidation of silicon The SOI interface surface state densities, as grown, were measured to be about 2*10/sup 11/ cm/sup -2/ eV/sup -1/ at midgap energies It is believed that H/sub 2/ from the epitaxial growth ambient is trapped at the interface and neutralizes surface states >

Half-micron CMOS on ultra-thin silicon on insulator

Abstract: A 0.5- mu m CMOS technology on ultrathin SIMOX SOI (silicon-on-insulator) material with silicon film thickness of 80 nm is studied. When compared with bulk devices the SOI NMOS devices showed a slightly reduced current-drive-capability, a small negative differential output conductance at high gate bias, and a strongly reduced breakdown voltage. Floating-substrate effects remain significant even for SOI devices on ultrathin material. The hot-carrier degradation of the SOI NMOS devices was significantly enhanced by electron injection in the buried oxide layer. The performance of ring oscillators on SOI material was excellent. Furthermore, fully functional 2K SRAM circuits were fabricated. The main advantages of ultrathin-film SOI seem to be the improved circuit properties and the simplified fabrication technology. The reduction of the floating-body effects in the devices on ultrathin-film SOI is required to make SOI a competitor to bulk material for future deep submicron CMOS. >

MOS thin film transistor

Abstract: Reduction of parasitic coupling capacitances which are otherwise formed between conventional NMOS transistor N type drain regions and the transistor's substrate and well regions is described by using a semiconductor-on-insulator (SOI) substrate and forming the NMOS transistor on a semiconductor (Si) substrate having a buried insulator forming a deep, lightly doped N type subsurface region beneath the conventional surface drain region (but not the source region) which contacts the buried insulator.

High-performance thin-film silicon-on-insulator CMOS transistors in porous anodized silicon

Abstract: Ultrathin-film silicon-on-insulator (SOI) CMOS transistors, produced in silicon islands 100 nm thick, formed by oxidation of porous anodized silicon, are described. Both n-channel and p-channel mobilities are similar to equivalent bulk values. Subthreshold slopes are less than 80 mV/decade and junction leakages are approximately 0.1 pA/ mu m. No kink is seen in the output characteristics of the n-channel transistors as the silicon film is fully depleted. A ring-oscillator gate delay of 161 ps has been achieved, at a power dissipation of 270 mu W/stage, for 1.5- mu m gate length. >

Novel silicon-on-insulator MOSFET for high-voltage integrated circuits

Abstract: A novel silicon-on-insulator MOSFET for high-voltage ICs is presented. Computer simulations are given to prove the high-voltage capability of the device structure. Also given is a practical implementation procedure.< >