Showing papers on "Static induction transistor published in 2006"

Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications

Abstract: A thin film transistor (TFT) includes a source electrode, a drain electrode, and a gate electrode. A gate insulator is coupled to the source electrode, drain electrode, and gate electrode. The gate insulator includes room temperature deposited high-K materials so as to allow said thin film transistor to operate at low operating voltage.

Semiconductor device, display device, and electronic device

Abstract: A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed. Consequently, a predetermined current can be supplied to the load such as a light-emitting element. Further, by changing the potential of a power supply line, a display device with a high duty ratio can be provided.

Improved subthreshold slope in an InAs nanowire heterostructure field-effect transistor.

Abstract: An n-type InAs/InAsP heterostructure nanowire field-effect transistor has been fabricated and compared with a homogeneous InAs field-effect transistor. For the same device geometry, by introduction...

Light emitting device, method of driving a light emitting device, element substrate, and electronic equipment

Abstract: A display device capable of obtaining a constant luminance without being influenced by temperature change is provided as well as a method of driving the display device. A current mirror circuit composed of a first transistor and a second transistor is provided in each pixel. The first transistor and second transistor of the current mirror circuit are connected such that their drain currents are kept almost equal irrespective of the level of load resistance. By controlling the OLED drive current using the current mirror circuit, a change in OLED drive current due to fluctuation in characteristics between transistors is avoided and a constant luminance is obtained without being influenced by temperature change.

Transistor with improved tip profile and method of manufacture thereof

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide

Simple and controlled single electron transistor based on doping modulation in silicon nanowires

Abstract: A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and therefore controlled by lithography. The source and drain capacitances have also been characterized. This design could be used to build more complex SET devices.

Field effect transistor and manufacturing method thereof

Abstract: A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.

Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array

Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Electronic Circuit, Method of Driving Electronic Circuit, Electro-Optical Device, Method of Driving Electro-Optical Device, and Electronic Apparatus

Abstract: To provide an electronic circuit, a method of driving the electronic circuit, an electro-optical device, a method of driving the electro-optical device and an electronic apparatus, capable of reducing deviations in threshold voltages of transistors. A pixel circuit 20 is constructed with three transistors of a driving transistor Trd, an adjusting transistor Trc and a switching transistor Trs, and two capacitors of a first capacitor C 1 and a second capacitor C 2 . Further, a source of the adjusting transistor Trc is connected to a voltage supply line VL for supplying a driving voltage Vdd through a control transistor Q in common with the sources of the adjusting transistors Trc of other pixel circuits, the voltage supply line VL being provided at the right end side of an active matrix part.

Pixel circuit of organic electroluminescent display device and method of driving the same

Abstract: A pixel circuit of an organic electroluminescent display device and a method of driving the same. In the pixel circuit, a capacitor has a first electrode connected to a gate of a driving transistor, and a second electrode connected to a drain of a switching transistor. Further, a compensation voltage applying transistor is connected to the second electrode of the capacitor. The compensation voltage applying transistor compensates for a difference in IR-drops of a power supply voltage in response to a previous emission control signal. Further, the compensation voltage applying transistor cuts off the compensation voltage in an initialization period, thereby preventing a source of a data voltage and a source of the compensation voltage from being shorted with each other. Additionally, a threshold voltage compensation transistor is connected between the gate and the drain of the driving transistor. Therefore, a difference in threshold voltages of driving transistors is compensated.

Merged MOS-bipolar capacitor memory cell

Abstract: A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and a collector region. The base region for the vertical bi-polar transistor serves as the source region for the vertical MOS transistor. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical MOS transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor. The base region for the vertical bi-polar transistor is coupled to a write data word line.

From poly line to transistor : Building BSIM models for non- rectangular transistors

Abstract: Non-rectangular transistors in today's advanced processes pose a potential problem between manufacturing and design as today's compact transistor models have only one length and one width parameter to describe the gate dimensions. The transistor model is the critical link between manufacturing and design and needs to account for across gate CD variation as corner rounding along with other 2D proximity effects become more pronounced. This is a complex problem as threshold voltage and leakage current have a very complex non-linear relationship with gate length. There have been efforts trying to model non-rectangular gates as transistors in parallel, but this approach suffers from the lack of accurate models for "slice transistors", which could potentially necessitate new circuit simulators with new sets of complex equations. This paper will propose a new approach that approximates a non-rectangular transistor with an equivalent rectangular transistor and hence does not require a new transistor model or significant changes to circuit simulators. Effective length extraction consists of breaking a non-rectangular transistor into rectangular slices and then taking a weighted average based on simulated slice currents in HSPICE. As long as a different effective length is used for delay and static power analysis, simulation results show that the equivalent rectangular transistor behaves the same as a non-rectangular transistor.

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Abstract: Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dry-etching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology

Pulse-frequency mode DC-DC converter circuit

Abstract: A step-down switching voltage regulator may operate in PFM mode based on peak current sense without requiring an external diode. The regulator may comprise a PMOS transistor and an NMOS transistor whose drains are coupled to a common output node and whose sources are coupled to high and low supply voltages, respectively, configured to develop a current in an inductor and generate an output voltage. A control circuit, coupled to the respective gates of the PMOS transistor and the NMOS transistor, may sense the current in the inductor (I L ), sense an attenuated version of the output voltage (VFB), and sense the polarity of the voltage (VX) developed at the common output node. The control circuit may turn on the PMOS transistor when the VFB falls below a reference voltage and VX remains positive with respect to the low supply voltage, and may turn off the PMOS transistor when I L reaches a specified value or when VFB exceeds the reference voltage. The control circuit may also turn on the NMOS transistor after the PMOS transistor is turned off and VX becomes negative with respect to the low supply voltage, and may turn off the NMOS transistor when VX becomes positive with respect to the low supply voltage.

Current sensing circuit

Abstract: A circuit arrangement for detecting a load current through a load includes a main transistor, a sensing transistor through which a load current flows that is a measure of the load current flowing through the main transistor, a means of resistance which is connected in series with the load path of the sensing transistor, a current source which is connected to a node which is arranged between the sensing transistor and the means of resistance, and a detector which detects the load current flowing through the main transistor by measuring the voltage across the means of resistance.

DC-DC converter and control circuit for DC-DC converter

Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.

MOS transistor device structure combining Si-trench and field plate structures for high voltage device

Abstract: A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field, therefore the transistor device has a relatively small size.

Low-frequency noise in SOI four-gate transistors

Abstract: Low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G/sup 4/-field-effect transistor] are reported. The noise power spectral density as a function of biasing conditions is presented and compared for surface and volume conduction modes. It is shown that, for the same drain current, the volume of the transistor generates less noise than its surface. The possible transition from carrier-number fluctuations to mobility fluctuations as the conducting channel is moved away from the surface toward the volume is also discussed.

Low dropout regulator with wide input voltage range

Abstract: A low dropout (LDO) regulator operates in wide input range. The LDO includes an N-type pass transistor and a P-type pass transistor for supplying power to the output terminal. The P-type pass transistor is connected with N-type pass transistor in parallel. Two error amplifiers control the gate terminals of the N-type pass transistor and P-type pass transistor to generate a first output voltage and a second output voltage. Thus, the first output voltage is generated when the input voltage is higher than a threshold voltage, and the second output voltage is generated when the input voltage is lower than the threshold voltage.

Multiple time programmable (mtp) pmos floating gate-based non-volatile memory device for a general purpose cmos technology with thick gate oxide

Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

Word line driver for DRAM embedded in a logic process

Abstract: A word line driver provided for accessing a DRAM cell embedded in conventional logic process and includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and p-type substrate are coupled to ground. The polarities can be reversed in another embodiment.

Semiconductor device, display device, and electronic appliance

Abstract: In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor.

Radio frequency power amplifier

Abstract: The present invention relates to a cascode radio frequency power amplifier, including at least two cascaded MOS transistors formed in a mutual substrate, where the bulk nodes of the transistors are isolated from each other and connected to the respective source of each transistor. The present invention also teaches that the drain of the topmost transistor is connected to the power supply through an inductive load, and that the gate of each upper transistor is equipped with a self-biasing circuit connected at least between the drain and the gate of the respective upper transistor.

Amplifying solid-state imaging device

Abstract: A signal charge is transferred from a photodiode (1) to a signal charge storage portion (8) through a depletion mode transfer transistor (2). A reset transistor (5) is connected between an input terminal and an output terminal of a MOS transistor (3). A vertical scanning circuit (25) always turns on the reset transistor (5) during a non-read period of the signal charge to make short circuit between input and output of the MOS transistor (3), thereby stopping amplification operation of the MOS transistor (3). An excessive signal charge generated in the photodiode (1) at the time of imaging a high-luminance subject is discharged to a vertical signal line (9) through a drain path constituted of the depletion mode transfer transistor (2), the signal charge storage portion (8) and the reset transistor (5). A switch circuit (13) performs switchover of the vertical signal line (9) between a reset voltage (VDD) and a constant current load transistor (4).

CMOS active pixel sensor and active pixel sensor array using fingered type source follower transistor

Abstract: A CMOS active pixel sensor includes a photodiode, a transmitting transistor, a reset transistor, a fingered type source follower transistor and a selecting transistor, where the photodiode generates charge in response to incident light, the transmitting transistor transmits the charge stored in the photodiode to a sensing node, the reset transistor, coupled to a power supply voltage, resets a voltage of the sensing node so that the sensing node has substantially a level of the power supply voltage, the fingered type source follower transistor amplifies the voltage of the sensing node, the selecting transistor transmits a voltage of a source electrode of the fingered type source follower transistor into an internal circuit in response to a selection signal, thus, the channel width of the source follower transistor may be increased, and the MOS device noise due to the source follower transistor may be reduced.

Semiconductor nanowire transistor

Abstract: A nanowire wrap-gate transistor is realised in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

Level shift circuit and power supply device

Abstract: In a level shift circuit including: an inverter circuit having a series circuit of a Pch-type transistor and an Nch-type transistor, which re connected between electrodes of a floating power supply; and a transistor Q1 in which a drain terminal and a source terminal are connected between an input terminal of the inverter circuit and a ground, wherein a drain terminal and source terminal of a transistor Q2 are connected between one terminal of the floating power supply and the drain of the transistor Q1, and a drain terminal and source terminal of a transistor Q3 are connected between a control terminal of the transistor Q2 and the ground.

Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage

Abstract: A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

Fast dynamic low-voltage current mirror with compensated error

Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.