Showing papers on "Strained silicon published in 1993"

Theoretical aspects of the luminescence of porous silicon.

Abstract: The luminescence in the visible range of porous silicon is analyzed in the hypothesis of quantum confinement. We calculate the electronic and optical properties of silicon crystallites and wires with sizes between 0 and 4.5 nm. The band-gap energies of such confined systems are in agreement with the photon energies observed in luminescence. We calculate the radiative recombination times of the confined excitons. We conclude that experimental nonradiative processes in porous silicon are more efficient than calculated radiative ones at T=300 K. The high photoluminescence efficiency of porous silicon is due to the small probability of finding a nonradiative recombination center in silicon nanocrystallites. Recently, it has been proposed that the low-temperature dependence of the experimental radiative decay time of the luminescence of porous silicon could be explained by the exchange splitting in the fundamental exciton. We show that the influence of the valley-orbit splitting cannot be excluded. The sharp optical-absorption edge above 3.0 eV is not proof of the molecular origin of the properties of porous silicon because silicon nanostructures present a similar absorption spectrum. We calculate the nonradiative capture of electrons or holes on silicon dangling bonds and show that it is very dependent on the confinement. We find that the presence of one dangling bond at the surface of a crystallite in porous silicon must destroy its luminescent properties above 1.1 eV but can produce a luminescence below 1.1 eV due to a radiative capture on the dangling bond.

Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

Abstract: A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

Silicon carbide power mosfet with floating field ring and floating field plate

Abstract: A silicon carbide power MOSFET device includes a first silicon carbide layer, epitaxially formed on the silicon carbide substrate of opposite conductivity type. A second silicon carbide layer of the same conductivity type as the substrate is formed on the first silicon carbide layer. A power field effect transistor is formed in the device region of the substrate and in the first and second silicon carbide layers thereover. At least one termination trench is formed in the termination region of the silicon carbide substrate, extending through the first and second silicon carbide layers thereover. The termination trench defines one or more isolated mesas in the termination region which act as floating field rings. The termination trenches are preferably insulator lined and filled with conductive material to form floating field plates. The outermost trench may be a deep trench which extends through the first and second silicon carbide layers and through the drift region of the silicon carbide substrate. Since the termination region is formed from the first and second silicon carbide layers in the termination region, a time consuming, high temperature diffusion to form a floating field ring is not necessary. Rather, the same epitaxial first and second silicon carbide layers which are used to form an FET in the device region may also be used to form the floating field ring in the termination region.

Identification of strained silicon layers at Si-SiO 2 interfaces and clean Si surfaces by nonlinear optical spectroscopy

Abstract: Optical second-harmonic and sum-frequency spectra of clean and oxidized Si(100) and Si(111) samples reveal a strong resonance band at 3.3 eV photon energy. It is concluded that the resonance arises from direct transitions between valence and conduction band states in a few monolayers of strained silicon at the Si-${\mathrm{SiO}}_{2}$ interface and at the selvedge of clean reconstructed silicon surfaces.

Semiconductor quantum dot light emitting/detecting devices

Abstract: A semiconductor light emitting/detecting device has a first doped silicon layer, an intrinsic silicon epitaxial layer formed on the first doped silicon layer, at least one quantum dot embedded within the intrinsic silicon epitaxial layer, and a second doped silicon layer formed on the second intrinsic silicon epitaxial layer.

Semiconductor heterostructure devices with strained semiconductor layers

Abstract: A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge x Si 1-x epitaxial layer overlain by a ungraded Ge x .sbsb.0 Si 1-x .sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.

Substrate for tensilely strained semiconductor

Abstract: A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Semiconductor thin film formed on a supporting substrate

Abstract: A semiconductor substrate is provided which has a semiconductor on insulator structure but in which can be formed a thin film integrated circuit having electrical characteristics and microstructure equal to or of greater density than a silicon integrated circuit formed using a bulk single crystal silicon wafer. The semiconductor substrate has a structure which is formed of a sequentially layered single crystal silicon thin film sandwiched between a thermally oxidized silicon film and a silicon oxide or silicon nitride film, an element smoothing layer, a fluoro-epoxy series resin adhesive layer, and a supporting substrate. The single crystal silicon thin film can have integrated circuit devices formed in a sub-micron geometry similar to that of a bulk single crystal silicon. A transparent glass or a bulk single crystal silicon wafer can be used as a supporting substrate. Therefore the semiconductor thin film can integrate a highly fine, dense and compact semiconductor integrated circuit or semiconductor optical element. The semiconductor thin film element has a transparent optical detection region or optical modulation region with 100 million pixels or more.

Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection

Abstract: A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide. In an alternative embodiment of the invention, fluorine atoms are introduced into the silicon substrate either as the sole barrier layer forming element (silicon fluoride) or prior to the formation of the thin silicon nitride region. The fluorine atoms form good strong silicon-fluorine bonds in the silicon substrate and thereby further enhance the hot electron suppression. In a third embodiment, nitrogen and fluorine are reacted in a rapid thermal processor to form a composite barrier layer of Si3 N4 and SF.

Method for forming silicon on a glass substrate

Abstract: A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Process for the production of accelerometers using silicon on insulator technology

Abstract: A process for the production of accelerometers using the silicon on insulator method. The process comprises the following stages: a) producing a conductive monocrystalline silicon film on a silicon substrate and separated from the latter by an insulating layer; b) etching the silicon film and the insulating layer up to the substrate in order to fix the shape of the mobile elements and the measuring devices; c) producing electric contacts for the measuring devices; d) partial elimination of the insulating layer in order to free the mobile elements, the remainder of the insulating layer rendering integral the substrate and the moving elements.

Valence energy‐band structure for strained group‐IV semiconductors

Abstract: A generic expression is presented for the valence‐band structure of strained group‐IV semiconductors (Si, Ge, and Si1−xGex alloys) that takes into account spin‐orbit coupling. The valence band is obtained using k⋅p perturbation theory coupled with deformation potential theory. The band‐structure equation is put into a simplified form that can be readily used, viz., ∑i=03 ∑j=03−iaijEkjk2i=0, where k is the wave‐vector magnitude, Ek is the energy at k, and the coefficients aij are functions of band parameters and strain components. The band structure of strained silicon is qualitatively analyzed in relation to the well‐established piezoresistivity coefficients. Furthermore, a new coefficient is introduced that describes the first‐order change in carrier concentration effective mass per unit applied stress for different stress directions.

Electron channelling contrast imaging of interfacial defects in strained silicon-germanium layers on silicon

Abstract: Images of defects at interfaces of strained Si1 - x Gex epilayers grown on bulk Si (001) substrates have been formed using the electron channelling contrast technique. The channelling images were obtained from bulk specimens using a highly efficient back scattered electron detector in an otherwise conventional scanning electron microscope equipped with a LaB6 electron source. Good channelling contrast was observed despite the defects in some cases being over 1 μm below the specimen surface. The spatial resolution was found to be too low to distinguish individual dislocations known to be grouped in closely spaced clusters. Instead the images show the distribution of these dislocation clusters. Contrast variations other than those explained by g.b = g.b x u = 0 criteria were found. Image simulations confirmed the experimental observation that image contrast is stronger whilst the incident beam is close to the perpendicular to the dislocation line direction. The technique is excellent at showing the...

Electrically programmable interconnect structure having a PECVD amorphous silicon element

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Method of producing a semiconductor device having two MIS transistor circuits

Abstract: After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation region of a high voltage drive circuit. Then, the gate oxide film in a low voltage drive circuit side is removed while maintaining this state. Then, after forming a gate oxide film on those surface sides, a polycrystalline silicon layer is subsequently formed in the surface side. After that, impurities are introduced into the polycrystalline silicon layer to provide it with electrical conduction, and then portions of polycrystalline silicon layers are left.

Die separation method for silicon on diamond circuit structures

Abstract: Silicon on diamond die 5 are separated by patterning the diamond layer 3 and sawing the silicon layer 4. The diamond layer 3 is patterned by known techniques including laser ablation or using a silicon dioxide mask to resist deposition of diamond material. Patterning may take place after formation of microelectronic devices in dies in the silicon layer, after a device water is bonded to a diamond layer but before formation of the devices, prior to joining the device wafer to the diamond layer.

Semiconductor substrate having a silicon-on-insulator structure and method of fabricating the same

Abstract: The invention provides a silicon-on-insulator semiconductor substrate structure and a method of fabricating the same. The structure includes a base silicon substrate, a mono-crystalline silicon film formed on the base silicon substrate in a predetermined region, a poly-crystalline silicon film formed on the base silicon substrate in opposite region to the predetermined region, an insulator film formed on the polycrystalline silicon film, and a mono-crystalline silicon layer overlaying both the insulator film and the mono-crystalline silicon film so that the mono-crystalline silicon layer is electrically connected to the base silicon substrate through the mono-crystalline silicon film. The mono-crystalline silicon film permits not the mono-crystalline silicon layer only but also the base silicon substrate to serve as active regions.

Schemes to form silicon-on-diamond structure

Abstract: Processes to produce Silicon-On-Diamond (SOD) Structures. In one process, two epitaxial layers are grown on a seed silicon wafer. The first layer is an etch stop layer and the second layer is an undoped silicon layer. A CVD diamond is deposited on top of this substrate, and covered with a thin layer of polysilicon. This structure is now bonded to another silicon handle wafer. The seed silicon layer and the etch stop layer are removed by mechanical means and chemical etching. The substrate consists of a silicon substrate, a polysilicon layer, a diamond layer and an undoped silicon layer. In a second process a diamond layer is deposited onto a SIMOX Wafer and polysilicon is deposited upon the diamond layer. A silicon wafer is bonded to the polysilicon layer and the SIMOX wafer less the silicon overlayer on the buried oxide is removed by grinding and etching to obtain silicon-on-diamond structure. A third process described uses a thick polysilicon as a handle wafer instead of bonding a silicon wafer as in processes I and II and uses the approach of the two processes described above. In this process a non-edge rounded silicon wafer as a starting substrate.

Method of making semiconductor quantum dot light emitting/detecting devices

Abstract: A semiconductor light emitting/detecting device has a first doped silicon layer, an intrinsic silicon epitaxial layer formed on the first doped silicon layer, at least one quantum dot embedded within the intrinsic silicon epitaxial layer, and a second doped silicon layer formed on the second intrinsic silicon epitaxial layer.

Silicon carbide wafer bonded to a silicon wafer

Abstract: A silicon carbide structure (10) and method capable of using existing silicon wafer fabrication facilities. A silicon wafer (20) is provided which has a first diameter. At least one silicon carbide wafer (30) is provided which has a given width and length (or diameter). The width and length (or diameter) of the silicon carbide wafer (30) are smaller than the diameter of the silicon wafer (20). The silicon wafer (20) and the silicon carbide wafer (30) are then bonded together. The bonding layer (58) may comprise silicon germanium, silicon dioxide, silicate glass or other materials. Structures such as MOSFET (62) may be then formed in silicon carbide wafer (30).

Investigation of silicon interstitial reactions with insulating films using the silicon wafer bonding technique

Abstract: The silicon wafer bonding technique of silicon implanted with oxygen (SIMOX) wafers is used to investigate the silicon interstitial reactions with a thin thermal oxide layer formed on the surface of one of the wafers before bonding. The silicon interstitials are generated by oxidation of the surface of selectively thinned bonded samples that form a silicon on insulator structure on the top of a SIMOX wafer. By monitoring the length of pregrown oxidation stacking faults we can calculate the diffusivity of the silicon interstitials transport vehicle in the thin oxide film for a temperature range widely used in silicon technology.

Method for fabrication of semiconductor device having polycrystalline silicon and metal silicides

Abstract: A method of fabricating a semiconductor device having a semiconductor substrate, a MOS transistor formed on one surface of the semiconductor substrate, and a capacitor is disclosed. The MOS has a gate electrode with a polycrystalline silicon layer and a metal silicide layer. The capacitor includes a first polycrystalline silicon layer which forms a lower electrode layer, an insulating interlayer, and a second polycrystalline silicon layer which forms an upper electrode, the first and second polycrystalline silicon layers sandwiching the insulating interlayer.

Method for fabricating semiconductor device in which threshold voltage shift and charge-pumping current are improved

Abstract: A method for fabricating a semiconductor device on a silicon substrate, consists of producing a silicon oxide film on the silicon substrate producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.

Selective formation of porous silicon

Abstract: A pattern of porous silicon is produced in the surface of a silicon substrate by forming a pattern of crystal defects in said surface, preferably by applying an ion milling beam through openings in a photoresist layer to the surface, and then exposing said surface to a stain etchant, such as HF:HNO3 :H2 O. The defected crystal will preferentially etch to form a pattern of porous silicon. When the amorphous content of the porous silicon exceeds 70% the porous silicon pattern emits visible light at room temperature.

Pulsed energy synthesis and doping of silicon carbide

Abstract: A method for producing beta silicon carbide thin films by co-depositing thin films of amorphous silicon and carbon onto a substrate, whereafter the films are irradiated by exposure to a pulsed energy source (e.g. excimer laser) to cause formation of the beta-SiC compound. Doped beta-SiC may be produced by introducing dopant gases during irradiation. Single layers up to a thickness of 0.5-1 micron have been produced, with thicker layers being produced by multiple processing steps. Since the electron transport properties of beta silicon carbide over a wide temperature range of 27°-730° C. is better than these properties of alpha silicon carbide, they have wide application, such as in high temperature semiconductors, including hetero-junction bipolar transistors and power devices, as well as in high bandgap solar arrays, ultra-hard coatings, light emitting diodes, sensors, etc.

Energy bands in quantum confined silicon light‐emitting diodes

Abstract: Measurements of the temperature dependence of the current‐voltage characteristics of heterojunction light‐emitting diodes fabricated by depositing indium tin oxide onto the surface of electrochemically etched p‐type silicon (porous silicon) are presented, and the results are compared with those for adjacent devices formed on nonprocessed bulk silicon The barrier height for the diodes which exhibit quantum confinement effects was determined to be 042 eV Unlike the bulk silicon devices, the diodes prepared on porous silicon did not manifest a photovoltaic effect These observations allow us to present a potential energy diagram for porous silicon heterojunction diodes which indicates barriers in both the conduction band and the valence band

MOS fabrication process, including deposition of a boron-doped diffusion source layer

Abstract: A method is described for making at least one MOS transistor on a silicon substrate. According to this method, a layer of a silicon dioxide material is formed on a principal surface of the substrate. The oxide layer is then patterned such that at least one source region and at least one drain region of the substrate are exposed. A layer of boron-doped germanium is then deposited on the exposed regions by RTCVD. The substrate is then heated such that boron diffuses from the germanium layer into the source and drain regions. The substrate principal surface can then be etched such that the germanium layer is removed with high selectivity.

Method for forming an oxide-filled trench in silicon carbide

Abstract: A method for forming an oxide-filled trench in silicon carbide includes the steps of amorphizing a portion of a monocrystalline silicon carbide substrate to thereby define an amorphous silicon carbide region in the substrate and then oxidizing the amorphous region to thereby form an oxide-filled trench in the substrate. Because of the enhanced rate of oxidation in the amorphous region as compared to the rate of oxidation of the surrounding monocrystalline silicon carbide regions at relatively low temperatures, the oxide-filled trench is generally defined by the lateral and vertical dimensions of the amorphous silicon carbide region. The amorphizing step includes the steps of masking an area on the face on the monocrystalline silicon carbide substrate to thereby expose a portion of the substrate wherein the amorphous region is to be formed and then directing ions to the face, such that the ions implant into the exposed portion of the substrate and create an amorphous silicon carbide region therein. The implanted ions are preferably selected from the group consisting of silicon, hydrogen, neon, helium, carbon and argon.

Transistors using crystalline silicon devices on glass

Abstract: A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.